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DDR4 Delay design for high speed signals (512 bits at 300 Mhz). IP to sell
Hi everyone, I've made that RTL design on a Kintex Ultrascale+ board with DDR4 (64 bits). Min delay is 128 Bytes but can be multiple of this. if someone is interested i'm selling this design.
u/Economy-Ad-3749 — 6 days ago