just finished my first single-cycle cpu in RISC-V ISA
hello risc-v community.
just this past year, i started to learn about hardware and wasn't exactly sure which path i wanted to take with my ee degree, but a few weeks ago I decided to go down the journey of designing a risc-v cpu, for no reason than to see if i could complete it from start to finish.
i had some prior experience with lc-3 assembly and systemverilog, and knew how to use ModelSim and Quartus for FPGA implementation, but this time I tried to learn new tools, namely Verilator and Icarus Verilog along with SDKWave.
the initial process was just me staring at a bunch of images of the datapath and reading Patterson and Hennessy's textbook through an online pdf. eventually, started to get the hang of it and drew up some diagrams. finally, decided to go on the verilog implementation and after 2.5 weeks of coding a bit of it daily, i have finished! i also included many comments in my code to explain some of my design choices for the modules.
here is the github repo URL: https://github.com/rohtakpat314/riscvcpu
and yes, I did use AI to help me with some of the roadblocks i faced. most of which occurred on the top module when wiring all of the modules together and in the data memory, when i was trying to add some additional levels of functionality with being able to write and read from specific upper and lower halves of the 32-bit data word or reading/writing from/to specific bytes of the word. I intend to generate some testbenches that are very verbose and concrete, and eventually add hazards/forwarding/pipelining for some throughput gains, but so far so good + excited to keep working.
cheers