Hi Everyone,

I'm Planning to apply for the Early Career ASIC Digital Design Engineer position at CERN and would really appreciate some feedback from people already working in the domain.

This is the Job Description from the page:

Your responsibilities

• Design, simulate, and verify the digital architecture of the next-generation ASIC front-end.
• Prepare RTL designs for tapeout using open-source EDA flows, including floorplanning and physical design preparation.
• Support post-fabrication bring-up, system characterisation, and functional/performance validation.
• Collaborate closely with analogue, verification, and SoC integration teams to ensure seamless system-level compatibility.

Your profile

• Hands-on experience with open-source ASIC EDA flows (Yosys, OpenROAD, LibreLane, etc.) from RTL to GDSII.
• Experience with floorplanning, constraint definition, and physical design preparation for tapeout.
• Post-tapeout prototype bring-up and hardware debugging experience is advantageous.
• Active contributions to open-source hardware projects or EDA toolchains are advantageous.

Your skills

• HDL design and simulation in VHDL, Verilog, or SystemVerilog.
• Good team player: collaboration skills across analogue, digital, verification, and SoC teams.
• Proficiency in Git, CI/CD pipelines, and automated verification workflows.
• Knowledge of RISC-V architecture.
• Familiarity with mixed-signal integration and digital interface protocols.
• Comfort with Linux-based development environments and scripting for automation (Python, Bash, etc.).

I've attached an anonymized version of the CV. Any feedback would be greatly appreciated.