Stuck on a 2-Layer Routing Maze: RGMII between MAC and PHY (No space, total ratsnest)
Hey there! im trying to design an Ethernet Circuit on a 2layer board, i know it sounds odd but that's what my company wanted.
Footprints:
U1: [MAC] PIC32CZ2051CA90144,
U2: [PHY] KSZ9031MNXCA,
J12: MAGJACK RJ45
D16, D15: TVS DIODE ARRAY(FOR ESD PROTECTION)
C36,C37: DECAPS FOR PHY
LEGEND:
RED: TOP COPPER LAYER.
BLUE: BOTTOM COPPER LAYER.
Im new to this ethernet/high speed designs. and ive heard that "we shouldn't place vias (with some exceptional cases), tight spacing between differential pairs with 100Ω impedance combined,. etc". But here from the very beginning i got stuck, as you can see the ratnets are criss-crossing. And ive checked both the Datasheets of my MAC and PHY as if there is any way to modify pins so that i can trace them without crossings, but they can't be modified.
i even tried to rotate U1 and U2 individually, but no use- this is the best possible way i can place.
Q1. CAN I PLACE VIAS AND TAKE THE TRACES FROM THE BOTTOM LAYER FOR THE 'A' SIDE PINS AND JOIN THEM AT 'C' & 'D' SIDES APPROPRIATELY???
Q2. IN IMAGE-2 RIGHT NEXT TO MY U2[PHY] YOU CAN SEE SOME DECAPS, AND YOU CAN SEE HOW I CONNECT THE GND TO THE DECAPS WITH BOTTOM TRACKS. IS THAT GOOD OR IT WAS BAD?
I will make the traces from my PHY to RJ45 as curved so i will do them at the end.
Finally, Please let me know if there is ANYTHING you would like to tell me.
Thankyou.