u/Indigo_Input

Does anyone with an RK3588 board want to help me find out if a distributed LLM inference board is worth building? (one script, ~15 min, no root)
▲ 2 r/OrangePI+1 crossposts

Does anyone with an RK3588 board want to help me find out if a distributed LLM inference board is worth building? (one script, ~15 min, no root)

I'm designing an open-hardware board that runs frontier-scale Mixture-of-Experts models by streaming expert weights off NVMe instead of holding them in RAM. Design stage , nothing has been built, and I'm trying hard not to build the wrong thing.

The whole design rests on one number I can't get without hardware: real NVMe read throughput on RK3588, at large block sizes, with O_DIRECT. My architecture assumes ~3.2 GB/s on a PCIe 3.0 x4 link. If that's actually 1.5 GB/s in practice, most of my timing figures are wrong and I'd rather find out now than after ordering PCBs.

I don't own an RK3588 board yet. Plenty of you do.

The ask: run one Python script on your board and paste the output. It:

  • is a single file, stdlib-only , no pip install, no repo clone
  • needs no root (it'll tell you what root would additionally buy)
  • is read-only apart from one temp file it creates and deletes
  • takes ~15 minutes, most of which is a sustained thermal test
  • prints one block you can paste back

What it measures:

  • Whether your CPU has SDOT (asimddp) , decides if llama.cpp's fast quantized kernels work
  • NVMe sequential + random read at 16 MB blocks, with and without O_DIRECT
  • PCIe link width and speed actually negotiated (I especially want to know if anyone's board reports x1 when it should be x4)
  • Sustained CPU frequency and temperature over 10 minutes, not burst , I care about the throttled number, not the marketing number

What's in it for you: you get a straight comparison of your board's real storage and thermal behaviour against everyone else's, which is annoyingly hard to find. I'll post the collated results back here regardless of what they say, including if they kill the idea.

Boards I'd love numbers from: Orange Pi 5 / 5 Plus / 5 Max, Radxa Rock 5B / 5C, FriendlyElec NanoPC-T6 / CM3588, ArmSoM, Banana Pi ,and honestly any RK3588 variant, plus non-RK3588 boards for comparison.

Repo (all design docs, MIT/CERN-OHL-P): https://github.com/Techburst36/swarm (Apologies in advance as the repo is a bit of a mess right now and might still have a few conflicting figures while the docs catch up.)

Script: swarm_bench.py in the repo root, plus a README explaining exactly what it does before you run it. Please do read it first , you shouldn't run a stranger's script on faith, and it's short enough to skim.

Happy to answer anything about the design in the comments.

Edit: made some changes as per u/fortean and u/12345myluggage feedback. The test had some real bugs that needed catching and some improvements to be made. Thank you!

u/Indigo_Input — 9 days ago
▲ 2 r/SBCs

Orange pi zero 3W: conflicting current specs for the 40-pin 5V power input, anyone know which is right?

Working on a HAT that powers the Zero 3W through the GPIO header (5V injection on pins 2/4), and I've hit a documentation conflict I can't resolve.

The official 40-pin header schematic annotates the 5V_Power pins as IN: 2A, OUT: MAX 0.5A. So 2A in, when something external is feeding the board.

But the manual (section 2.12, "Instructions for powering the 5V pin in the 40 pin interface") says to make sure your supply meets the board's power requirements, and elsewhere the board's stated requirement is 5V/3A.

So which is it? Is that 2A a real limit on the trace or connector for the GPIO path, or is it a conservative annotation and the pin can actually carry the full 3A the board might want under load?

This matters because I'm designing in an eFuse for current limiting and I need to pick a trip point. Set it at 2A and I might starve the board under heavy CPU+GPU+NPU load. Set it at 3A and if that 2A annotation reflects a real physical limit, I could cook something.

Has anyone actually measured peak current draw on this board under real load? The one data point I've seen is ~6.5W at 100% CPU (~1.3A at 5V), but that was CPU-only, no GPU testing.

Also curious if anyone's actually run this board off GPIO power long-term rather than USB-C, and whether it was stable under load.

reddit.com
u/Indigo_Input — 19 days ago

Zero 3W: conflicting current specs for the 40-pin 5V power input, anyone know which is right?

Working on a HAT that powers the Zero 3W through the GPIO header (5V injection on pins 2/4), and I've hit a documentation conflict I can't resolve.

The official 40-pin header schematic annotates the 5V_Power pins as IN: 2A, OUT: MAX 0.5A. So 2A in, when something external is feeding the board.

But the manual (section 2.12, "Instructions for powering the 5V pin in the 40 pin interface") says to make sure your supply meets the board's power requirements, and elsewhere the board's stated requirement is 5V/3A.

So which is it? Is that 2A a real limit on the trace or connector for the GPIO path, or is it a conservative annotation and the pin can actually carry the full 3A the board might want under load?

This matters because I'm designing in an eFuse for current limiting and I need to pick a trip point. Set it at 2A and I might starve the board under heavy CPU+GPU+NPU load. Set it at 3A and if that 2A annotation reflects a real physical limit, I could cook something.

Has anyone actually measured peak current draw on this board under real load? The one data point I've seen is ~6.5W at 100% CPU (~1.3A at 5V), but that was CPU-only, no GPU testing.

Also curious if anyone's actually run this board off GPIO power long-term rather than USB-C, and whether it was stable under load.

reddit.com
u/Indigo_Input — 19 days ago

Board design done, DRC-clean, files are up, moving into a GPIO passthrough HAT next

Update on the PCIe-to-M.2 adapter from my earlier post. Schematic and PCB layout are done. ERC and DRC both come back clean, Gerbers are exported and JLCPCB's own parser confirms the board renders correctly. I have a saved quote ready to order whenever the budget lines up.

Full disclosure: I'm not an EE, not a professional, just someone learning by doing. I've been careful and this has passed every check I know to run, but "passed DRC" isn't the same as "guaranteed to work."

On the big open question from my last post: PCIe enumeration hasn't been confirmed on the Zero 3W specifically yet. But I dug into it more and it's not a total unknown either. The same A733 chip and the same vendor PCIe driver has been documented working on sibling boards (Orange Pi 4 Pro, Radxa Cubie A7Z/A7A/A7S), NVMe does enumerate, though there's a known Gen3 speed-change bug that trips up some drives (Phison controllers especially), fixable by forcing Gen1 or using a WD drive instead. So there's real reason to think this can work, just not proof yet on this exact board.

Instead of sitting on the design waiting for money or answers, everything's public now: KiCad source files and Gerbers, open, do whatever you want with them.

Repo: https://github.com/Techburst36/orangepi-zero3w-m2-carrier

If you can read a schematic, please look it over. If something's wrong, tell me. If you've got the budget to print and test before I do, please do, I'd genuinely rather have someone else get the real answer sooner than have this sit in a drawer waiting on me.

Not trying to monetize this or gatekeep it, just filling a gap, since nobody's published a PCIe-to-M.2 adapter for this specific board yet.

Next up: starting design work on a GPIO passthrough HAT variant, purely on the design side for now since I still don't have confirmation PCIe actually trains on this SoC. Will keep this thread updated as that moves along.

u/Indigo_Input — 20 days ago
▲ 6 r/SBCs

[Zero 3W] Building a custom PCIe-to-M.2 adapter — looking for anyone who's touched the PCIe FPC connector, kernel PCIe status, or GPIO 5V injection

Hey all, I'm designing a custom PCB adapter for the Zero 3W's PCIe FPC connector (FPC16-ZHX_H15-L1-H, per the official schematic) to break it out to an M.2 M-key slot, sized to also double as a mounting carrier plate matching the board's hole spacing. Goal is NVMe storage expansion first, with an eye toward AI accelerator cards (Hailo-10H) as a stretch goal later.

Before I finalize the board and order a first run, I'm hoping someone in this community has hands-on data on a few open questions I haven't been able to resolve from documentation alone:

1. Has anyone gotten anything enumerating over the PCIe FPC connector yet? Even just a plain NVMe SSD via a generic FPC adapter. I want to confirm the PCIe controller actually comes up cleanly in root-complex mode under Armbian/the stock BSP before I commit to a board run. If you've tried and it didn't work (or worked with caveats), that's just as useful to know.

2. What kernel/BSP are people actually running for PCIe support? I know mainline upstreaming for A733 is actively in progress (saw the recent patch series for pinctrl/RTC/clocks), but I'm assuming most of us are on a vendor BSP kernel day-to-day. Anyone know if PCIe root-complex support is enabled and stable in the current Armbian/Xunlong images, or is it still rough?

3. Any known PCIe controller quirks on A733 specifically? Older Allwinner chips (H6) reportedly needed a hypervisor-level MMIO workaround for their PCIe controller. Has anyone hit anything similar on A733, or does it behave as a clean standard DesignWare PCIe implementation?

4. Is injecting 5V back into the board via the GPIO header's 5V pins safe on this board? I'm considering an M5Stack-PiHat-style single-cable design (board powers itself AND feeds accelerator power back through the GPIO header, like the official Pi 5 AI HAT+ pattern). On Pi 5 this is an explicitly documented, supported use case. I can't find anything in Xunlong's docs confirming the AXP318 PMIC on the Zero 3W is designed to safely handle reverse power injection via GPIO the same way. Anyone tried this or know if it's safe / risky / a bad idea?

5. Real-world total board power draw, is 3A genuinely the ceiling? Schematic labels the board 5V/3A total. Anyone measured real idle/load current draw with a USB power meter? Between the board under load, an NVMe SSD, and potentially a ~2.5W typical draw NPU later, I'm trying to nail down actual headroom before I decide how to handle power delivery on the carrier board.

6. Has anyone seen PCIe link training issues / Gen 1 fallbacks? I found a boot log from an A733 board (Cubie A7Z) showing Link up timeout / Speed change timeout / PCIe speed of Gen1 during boot. Has anyone else seen the A733 struggle to train at Gen 3 (or even Gen 2) and fall back to Gen 1, or is that an isolated hardware/board quirk?

Board design itself (FPC connector footprint, M.2 slot, mounting holes) is done and validated mechanically in Fusion — just trying to de-risk the electrical/software side before committing to a PCB order. Will share the KiCad files once it's built and working, since I haven't found an existing PCIe-to-M.2 adapter for this board anywhere.

Thanks in advance to anyone who's poked at this corner of the board.

reddit.com
u/Indigo_Input — 22 days ago

[Zero 3W] Building a custom PCIe-to-M.2 adapter — looking for anyone who's touched the PCIe FPC connector, kernel PCIe status, or GPIO 5V injection

Hey all ,I'm designing a custom PCB adapter for the Zero 3W's PCIe FPC connector (FPC16-ZHX_H15-L1-H, per the official schematic) to break it out to an M.2 M-key slot, sized to also double as a mounting carrier plate matching the board's hole spacing. Goal is NVMe storage expansion first, with an eye toward AI accelerator cards (Hailo-10H) as a stretch goal later.

Before I finalize the board and order a first run, I'm hoping someone in this community has hands-on data on a few open questions I haven't been able to resolve from documentation alone:

1. Has anyone gotten anything enumerating over the PCIe FPC connector yet? Even just a plain NVMe SSD via a generic FPC adapter. I want to confirm the PCIe controller actually comes up cleanly in root-complex mode under Armbian/the stock BSP before I commit to a board run. If you've tried and it didn't work (or worked with caveats), that's just as useful to know.

2. What kernel/BSP are people actually running for PCIe support? I know mainline upstreaming for A733 is actively in progress (saw the recent patch series for pinctrl/RTC/clocks), but I'm assuming most of us are on a vendor BSP kernel day-to-day. Anyone know if PCIe root-complex support is enabled and stable in the current Armbian/Xunlong images, or is it still rough?

3. Any known PCIe controller quirks on A733 specifically? Older Allwinner chips (H6) reportedly needed a hypervisor-level MMIO workaround for their PCIe controller. Has anyone hit anything similar on A733, or does it behave as a clean standard DesignWare PCIe implementation?

4. Is injecting 5V back into the board via the GPIO header's 5V pins safe on this board? I'm considering an M5Stack-PiHat-style single-cable design (board powers itself AND feeds accelerator power back through the GPIO header, like the official Pi 5 AI HAT+ pattern). On Pi 5 this is an explicitly documented, supported use case. I can't find anything in Xunlong's docs confirming the AXP318 PMIC on the Zero 3W is designed/protected for reverse power injection via GPIO the same way. Anyone tried this or know if it's safe / risky / a bad idea?

5. Real-world total board power draw , is 3A genuinely the ceiling? Schematic labels the board 5V/3A total. Anyone measured real idle/load current draw with a USB power meter? Trying to nail down actual headroom before I size a separate accelerator power supply.

Edit: 6. Has anyone seen PCIe link training issues / Gen 1 fallbacks? I found a boot log from an A733 board (Cubie A7Z) showing Link up timeout / Speed change timeout / PCIe speed of Gen1 during boot. Has anyone else seen the A733 struggle to train at Gen 3 (or even Gen 2) and fall back to Gen 1, or is that an isolated hardware/board quirk?

Board design itself (FPC connector footprint, M.2 slot, mounting holes) is done and validated mechanically in Fusion , just trying to de-risk the electrical/software side before committing to a PCB order. Will share the KiCad files once it's built and working, since I haven't found an existing PCIe-to-M.2 adapter for this board anywhere.

Thanks in advance to anyone who's poked at this corner of the board.

reddit.com
u/Indigo_Input — 22 days ago

Questions regarding personal project and orange pi zero 2w/3w

Hi everyone, first time posting here and i come with a few questions!

I've just recently started dabbling into sbc's and logically started a project with raspberry pi as my go to, but saw that the prices for the raspberry zero 2w were.... kinda insane right now for a measly 512 mb of RAM. So I've been considering the orange pi zero 2w as a replacement.

The project is what i think is ... sort of a cyberdeck? im really new to this terminology. That said, I was wondering: would the pi sugar 3 1200mah baterry with pogo connection work with either of these boards since they seem to have pretty similar gpio schematics to the raspbery pi zero 2w? https://www.pisugar.com/products/pisugar-3-raspberry-pi-zero-battery

also, would this screen specifically work with the 2w/3w:https://www.waveshare.com/product/displays/lcd-oled/lcd-oled-2/3.5inch-dpi-lcd.html

thanks in advance for any guidance!

u/Indigo_Input — 25 days ago