Q2 MD&A the CMOS line is the number nobody is talking about
Q2 MD&A dropped Aug 14. Everyone’s looking at the SecureKey IUT listing, which is fair. But I went through the R&D project breakdown line by line and there’s one number I haven’t seen discussed here.
Not thousand. One thousand five hundred and eighty-four dollars. Last quarter it was $1,750. Cumulative since the project started: $133,203.
For comparison, here’s what the other projects got in Q2:
QBUCS (JMEM): $161,288
FIPS: $136,700
SecureKey: $89,581
SDK: $86,651
EaaS: $48,992
CMOS: $1,584
CMOS got 0.3% of the R&D budget this quarter.
The language didn’t move either. I pulled up Q1 and compared it side by side. The CMOS section reads word for word the same. “Current focus is on stabilizing the amplifier.” “Additional design iterations ongoing.” “Full chip integration, fabrication and system validation expected within next 6-12 months.” That last one matters. In Q1 (filed as of March 31) “6-12 months” meant roughly Sept 2026 to March 2027. In Q2 (as of June 30) the same sentence now means Dec 2026 to June 2027. The target slid a full quarter without a dollar spent.
Before anyone says they’re broke they’re not. Cash and marketable securities: $33.5M. They spent $136,700 on FIPS in a single quarter, a 6x increase from Q1. The money exists. It went somewhere else.
Now the part where I might be wrong, and I want pushback on this specifically.
The MD&A says CMOS work is being done “with l’ÉTS.” If ÉTS is carrying the design work grad students, professors, CMC Microsystems subsidised EDA tools then design costs genuinely wouldn’t show up on QNC’s books. That’s a real explanation and I’m not dismissing it.
But here’s my issue with it: a tape-out costs actual money regardless of who does the design. A wafer doesn’t get fabricated on academic goodwill. Even a shared MPW shuttle run at 65nm runs into the tens of thousands. A full mask set is six figures. If a fabrication event had happened in Q2, something would have hit the line. $1,584 doesn’t cover it.
So the cumulative number tells us something too. $133K total, for the entire life of the project. That’s not consistent with multiple commercial respins. If anything it suggests we’re at or before the first full-chip fabrication, not several iterations deep. Which brings up the thing I can’t reconcile. The May 2025 PR said the “65-nm finalized design has been submitted for fabrication to TSMC.” But the Q2 MD&A still lists milestone, 3 full chip integration, as ongoing. Also worth noting: milestone 2 (ADC/DAC) is described as “completed, fabricated and tested.” Milestone 1 (the amplifier) is only “completed and tested.” No “fabricated.”
Respins are normal. First-silicon-perfect is maybe a 30% outcome in complex analog. Anyone treating “they had to iterate” as a scandal doesn’t know how chips get built. And honestly, spending money on a respin would be a good sign, not a bad one. Nobody pays for a wafer run on a design they don’t believe in. Spending is a commitment signal. What worries me is the opposite: not spending. That means either the design still isn’t converging in simulation, or the work sits entirely on the academic side, or CMOS dropped down the priority list. None of those are as good as “they paid for a run.”
Same line. If it’s still $1-3K, that’s three straight quarters and I’d stop calling it a pause. If it jumps to $20-80K, that reads like an MPW shuttle run and I’d take it as a positive. $200K+ would be a real commercial tape-out and that’s a strong signal.
The pattern that would actually concern me is a spike followed by two quarters of silence. That’s the shape of a fab run that came back disappointing. Not selling, not telling anyone else what to do. The FIPS line moving from $22K to $136K is real and it lines up with the IUT listing, so the SecureKey side is genuinely being funded. That part is working. But the CMOS chip is the thing most of us bought this story for, and right now it’s getting 0.3% of the R&D budget. That’s worth saying out loud.
If someone has better information on the ÉTS arrangement whether there’s a separate CMC or grant budget covering fabrication outside QNC’s books I’d genuinely like to see it. That would change how I read this.
Numbers are all from the Q2 MD&A on SEDAR+, section 1.4, filed Aug 14 2026.