u/Zeekiosk

Hi everyone, I'm having issues with PSRAM on my new board. I'd really appreciate help with this since I'm at my wits end, and I need the extra PSRAM for my application (Digital Audio Player). Here's all the details:

Setup

• Custom RP2350-based board, 1.8V IO, PSRAM is the APS6404L-SQRH-ZR
• PSRAM on QMI CS1, CS routed to PIN_0
• System clock 150 MHz, QMI divisor 2 → 75 MHz SCK, rxdelay 2
• Same firmware/init sequence runs fine on a Pimoroni Pico Plus 2 (which uses CS on PIN_47)
• embassy-rp PSRAM driver (from my fork) QPI mode, 0xEB read / tried both 0x38 and 0x02 for write, 24 dummy cycles
• Minimal reproduction: https://github.com/tsar-boomba/dap-proto-test
• My embassy-rp fork (doesn't modify any core logic of the PSRAM driver): https://github.com/tsar-boomba/embassy/blob/main/embassy-rp/src/psram.rs

What works

• PSRAM device verification (KGD/EID read) passes — reports correct 8MB size
• QMI register config reads back correct (timing, rfmt, rcmd, wfmt, wcmd all as expected)
• Write via uncached alias (0x1500_0000) then read back via cached alias (0x1100_0000): full 8MB, passes every time
• Writes via uncached alias work

What fails

• Pretty much anything not mentioned above
• Sequential write only via cached alias (0x1100_0000) appears to hang. I can see it running the write loop with gdb, but it never completes (or takes a really long time)
• HEAP.init writing bookkeeping into PSRAM base: hard faults (PC=0x0, branch through null)
• Failures are nondeterministic. Same build will sometimes hang, sometimes fault, sometimes get further before dying

Failures Seen

• HardFault with PC=0x00000000, LR=0x00000012 (branch through null/garbage pointer)
• HardFault with PC in valid flash, faulting code touching PSRAM (r2=0x11000000)
• Sometimes pure indefinite hang, no fault. Could mean QMI stalled with CS1 asserted
• Sometimes things will panic that don't panic on the pimoroni board
• Just all the classic signs of memory corruption all over the place

Key characteristics

• Read path through cache works completely. Write path through cache is what breaks
• nondeterministic rather than a hard logic error
• cooldown 0 made no difference
• Pretty sure it's not a software difference since identical firmware works on Pimoroni Pico Plus 2 (only difference is pads are set to 3.3v on pimoroni)

Things already tried with no effect

• 0x38 vs 0x02 write command
• QSPI pads explicitly set to 1.8V, drive strength reduced to 4mA
• CS pad (PIN_0) drive strength reduced to 4mA, slewfast off
• cooldown 0 vs 1

Board notes / suspected differences vs working Pimoroni board

• 10k pull-up on CS instead of Pimoroni's 100k
• QSPI traces shorter than Pimoroni, 50 ohm impedance;,data line length mismatch: shortest is 7.3mm, longest is 13.7mm
• Schematic otherwise matches reference

I'm really at my wits end with this! I get the feeling I messed up the layout somehow, but I can't really test it since I don't have access to an oscilloscope at the moment. Thanks for taking a look!