u/gdevic

I built a scientific calculator from scratch: custom PCB, custom FPGA firmware, and a CPU I designed myself in Verilog.

The physical build: a custom main board and keypad PCBs designed in EasyEDA and manufactured by JLCPCB, an Altera Cyclone II FPGA as the brain, an LCD display, battery with charging circuit, and two ROM-flashing connectors on the sides to update the firmware.

Under the hood it runs a nibble-oriented CPU I designed specifically for BCD arithmetic: the way decimal calculators should work internally. I then wrote ~4K of machine code implementing the full set of scientific functions: trig, logarithms, complex numbers, statistics, all verified to 14 significant digits against a dedicated test suite.

The full stack:

• Custom CPU in Verilog: Harvard architecture, 12-bit ISA, 8 registers, hardware fault detection
• Hand-written microcode assembler in Python
• Verilator + Qt simulation framework for development and debugging
• Custom PCB (EasyEDA / JLCPCB), battery, charging circuit, 3D printed case

The finished device is sitting on my desk.

Live WebAssembly demo (runs the actual Verilog + microcode in your browser): https://baltazarstudios.com/files/calculator-d/Calculator.html

Write-up: https://baltazarstudios.com

Source: https://github.com/gdevic/FPGA-Calculator

Hackaday: https://hackaday.com/2026/05/13/build-the-cpu-then-build-the-calculator/

Happy to answer questions about the PCB design, the FPGA setup, or anything else.

I designed and built a scientific calculator on an FPGA, using a custom nibble-oriented CPU I wrote in Verilog. Then I wrote ~4K of its machine code that implemented a large set of operations you'd normally find in a calculator. All operations are verified against long-doubles with a dedicated test suite.

The calculator uses BCD arithmetic: one decimal digit per 4-bit nibble. Standard byte-oriented CPUs fight that layout constantly. This CPU has 4 bits as the natural data width, memory is nibble-addressable, and walking through a 16-digit mantissa is just a loop.

What I built:

• Custom nibble-oriented CPU in Verilog: Harvard architecture, 12-bit ISA, 8-state FSM, 8 registers, hardware stack guard with a FAULT state, interrupts, ...
• Two-pass assembler in Python (~700 lines)
• Verilator + Qt simulation framework: same Verilog runs in simulation, GUI debugger, WebAssembly, and on real FPGA hardware
• CORDIC for trig, BCD arithmetic verified to 14 significant digits
• Scripting language on top of the microcode for adding more complex functions
• Custom PCB (EasyEDA / JLCPCB), battery, charging circuit; 3D printed enclosure

Synthesized on a Cyclone II EP2C5. The finished device is on my desk.

Write-up: https://baltazarstudios.com

Source: https://github.com/gdevic/FPGA-Calculator

Live demo (actual Verilog + microcode compiled to WebAssembly): https://baltazarstudios.com/files/calculator-d/Calculator.html

Hackaday: https://hackaday.com/2026/05/13/build-the-cpu-then-build-the-calculator/

Happy to discuss any of the architecture decisions.