
RX 7800 XT 16 GB + 64 GB DDR4: 985tk/s prefill and ~65 tok/s decode with Strata and Qwen3.8-Flash-Next IQ3_XXS
Sharing some results from my own PC running [Strata](https://github.com/Niko1221/Strata) with the HIP backend. The model is **Qwen3.8-Flash-Next-GSQ-RCO-IQ3_XXS**. These are engine timings from real chat sessions, including generated reasoning tokens.
My setup:
- AMD Radeon RX 7800 XT, 16 GB VRAM (`gfx1101`)
- Ryzen 7 5800X3D, 8 cores / 16 threads, AVX2
- 64 GB DDR4 RAM
- Ubuntu 26.04.1 LTS, kernel 7.0.0-38-generic
- Strata 0.1.42, built locally for HIP; system HIP 7.15 and hipBLASLt 1.4.1
In my latest session, the prompt/context grew from **41,709 to 75,100 tokens** across **54 completed requests**. The engine generated **18,806 tokens in 289.772 seconds of decode time**:
| Measurement | Result |
| Aggregate decode throughput, total tokens / total decode time | **64.9 tok/s** |
| Median throughput per request | **66.4 tok/s** |
| Per-request decode range | **56.1–82.8 tok/s** |
| Fresh 41,709-token prompt, zero reused tokens | **985.8 tok/s prefill** |
Most later turns reused the conversation prefix, so their prompt timings should not be treated as full-context prefill benchmarks. The expert cache was also warmed by the conversation.
Other fresh-prompt measurements with this setup were **912.9 tok/s at 6,731 tokens**, **1,004.6 tok/s at 76,599 tokens**, and **791.0 tok/s at 116,392 tokens**. I also had a slower 38,790-token read at **509.8 tok/s**. Across all 61 completed tail-skip-enabled requests in today's log, including the slower sessions and much longer generations, aggregate decode was **52.7 tok/s**. The ~65 figure refers specifically to the latest 54-request session.
The settings used for these runs:
--expert-cache auto
--prefill auto
--max-context 131072
--kv int8
--spec 4
--spec-min-p 0.70
--pcie-frac 0.35
--adapt-every 1
--adapt-swaps 160
--adapt-decay 0.97
MTP was enabled. The default CPU pool used 7 workers plus the host thread. The PCIe probe measured about 27.9 GB/s, but decode calibration selected `--pcie-frac 0.35` rather than the automatic 0.55. The engine loaded **39.97 GiB of expert weights into host RAM** and cached **5,048 experts / 8.19 GiB** in VRAM at startup.
I also used:
export STRATA_SH_STREAM=1
export STRATA_ROUTE_TAIL_SKIP=7
export STRATA_HIPBLASLT_TUNING="/path/to/strata-gfx1101-hipblaslt.txt"
The hipBLASLt table was generated locally for **gfx1101 + hipBLASLt 1.4.1**, with 26 rows. The log confirms that it was loaded. Those solution IDs are tied to that architecture and library version.
The project's **experimental speed projection** was also enabled at strength 1.0, layers 4–44, using `--cvec-mode project --cvec-dir per-layer`.
One informal comparison on the same accounting/Python prompt gave **50.8 tok/s without route tail skip** and **56.7 tok/s with it**. Both visible answers were correct, but the generated lengths and expert-cache hit rates differed, so this is not a controlled estimate of the switch's benefit. Tail skip changes the computation and can change the answer; I have not run a comprehensive quality benchmark.
I hit one watchdog stall during an earlier stock-config run. The latest 54-request session completed without a reported stall. This is a report of my own measurements, rather than a claim that these settings will be fastest or stable on every AMD setup.