u/tinkering_around

Fabrication errors in foundry tapeout for PICs

I am trying to do a sensitivity analysis for a PIC and am interested to know what are the major fabrication errors(i know few common ones like side wall roughness, side wall angles, slab thickness variation) that occur for foundry tape out and how they are modeled in sensitivity analysis (monte carlo?)?

I hope people with experience help me with this.

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u/tinkering_around — 8 days ago

Can we submit active devices in the UBCx: Silicon Photonics Design, Fabrication and Data Analysis?

Now I know that the feedback and reviews for this course have been asked before ample number of times on this subreddit, but I was curious to know if we can also submit active device for this course?

I was primarily thinking of using metal heaters and some components with doping.

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u/tinkering_around — 8 days ago
▲ 13 r/SiliconPhotonics+1 crossposts

What do you all think about Silicon Photonics Inverse Design ?

I am working on a photonic inverse design project for foundry tapeout but I am curious to know what y'all think about it.

While I understand there are various challenges which come with it from the perspective of yield/fabrication robustness I am curious to what are the major barriers that would prevent people from adopting it commercially.

While in the conventional design approach we can add heaters to help with post fabrication correction which may be challenging with inverse designed devices. But at the same time inverse design can potentially reduce the device footprint?(How important is the footprint issue currently?)

I see plenty of papers on inverse designed Broadband 50:50 couplers but for tapeout, people still stick to the conventional parallel waveguide couples even though the footprint seems bigger.

I also see plenty of Inverse designed WDM, why are they not widely used in say the MRR based transceivers?

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u/tinkering_around — 12 days ago