r/OpenChipDesignIndia

Hi, I'm a final year UG student , I find that whenever I apply to any job my resume is average , meaning it doesn't stand out , what will make my resume standout , Now I don't mean generic resume optimizations, Maybe some hackathon victories? What's the factor that makes my resume really standout?

Something that when you see , it grabs your attention.makes it extraordinary?

My prefrence and project work is mainly on Digital Design ,Verilog RTL

Welcome to OpenChipDesignIndia.

This community is for students, engineers, educators, makers, and semiconductor enthusiasts who want to learn chip design by actually building.

Here, we discuss VLSI, RTL design, Verilog, RISC-V, FPGA, physical design, open-source EDA tools, RTL-to-GDS flows, tapeout journeys, student projects, semiconductor careers, and India’s growing chip design ecosystem.

The goal is simple: make chip design more practical, visible, and accessible for everyone.

You are welcome to:

Ask beginner or advanced technical questions
Share your chip design, FPGA, RISC-V, or embedded projects
Discuss career doubts in VLSI, physical design, RTL, verification, and semiconductor roles
Post useful tools, tutorials, papers, repositories, and learning resources
Share your progress, failures, bugs, fixes, and lessons learned
Discuss how India can build a stronger semiconductor talent pipeline

A few expectations:

Be respectful. Many people here are learning.
Avoid gatekeeping. Simple questions are welcome.
Give practical answers whenever possible.
No spam, fake hype, or low-effort self-promotion.
Promote learning, building, and honest technical discussion.

Whether you are a school student blinking your first LED on an FPGA, an engineering student learning Verilog, a working professional entering VLSI, a faculty member building a lab, or a chip designer sharing experience — you belong here.

Let’s learn chips. Build chips. Share chips.

Welcome to OpenChipDesignIndia.