Advice on FPGA ADC streaming design flow
Hi all, I recently put together a Zedboard FPGA dev board and an AD9226 ADC module. I’m sampling the data and sending to my computer using UDP. This is a project for me to learn some more, no commercial use and I’d be happy to open source as-is or later down the line once a few things are fixed.
But for now I’m really just looking for advice or input on how professionals or experience FPGA devs would process the data and get it sent out.
My currently flow is:
12-bit parallel ADC input -> input sample registers -> simple 2-sample pair buffer -> 12-bit-to-byte packer -> AXI4-Stream frame generator -> AXI DMA S2MM stream input -> AXI DMA internal buffering -> AXI memory-mapped writes -> PS DDR buffer -> ARM/lwIP reads DDR buffer -> UDP packet sent over Gigabit Ethernet
All signal processing is done on the computer in C++ with some libraries for the GUI and this allowed me to easily process for both the time or frequency domain. I would like to add the option for the FPGA to FFT data before sending in the future too.
Any advice or feedback is greatly appreciated!