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r/FPGA

▲ 8 r/FPGA

Struggling to Write I2C RTL Code — Need Guidance

I’m currently learning I2C protocol and I understand the theoretical concepts like start/stop condition, ACK/NACK, addressing, read/write operations, etc.

But when it comes to writing the actual Verilog/VHDL code for an I2C controller, I’m getting stuck and confused about how to properly design the FSM and handle timing/control logic.

I’ve been trying to implement it on my own but I’m struggling to move forward.

Can anyone share guidance, resources, sample RTL structure, or explain how you approached coding an I2C master/slave design?

Any help would be really appreciated.

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u/Immediate_Try_8631 — 16 hours ago
▲ 2 r/FPGA+1 crossposts

Which linux distro is best for vlsi based software tools

Hi guys i wanted to use softwares such as xilinix vivado,intel quartus prime,modelsim and i know there are linux versions of these software exists but my question is which distro is most supported for these kind of eda and fpga related softwares?

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u/jeevaks — 19 hours ago
▲ 5 r/FPGA+1 crossposts

Efficient image window vectorization for CNN accelerator (systolic array design)

Hi everyone,

In CNN accelerators, we often use systolic arrays to speed up matrix multiplication and reduce overall computation latency. This approach works very well for convolution once the data is already in a vector/matrix form.

However, I feel that another major bottleneck is the process of sliding the filter over the image and converting each local window into a vector before feeding it into the systolic array.

I would really like to hear your ideas and approaches for efficiently vectorizing image windows in hardware. Are there any optimized architectures or scheduling techniques you use to reduce this overhead?

In my current design:

  • Input: 28×28 image
  • Filters: 10 kernels of size 3×3
  • Stride: 1, Padding: 1

Even with the systolic array accelerating multiplication, the full convolution still takes around 8000 clock cycles, and I suspect the window extraction / data feeding (im2col-like process) is a major contributor.

Has anyone worked on reducing this “windowing / im2col” overhead or implemented more efficient streaming or line-buffer based approaches?

I’d really appreciate any thoughts or design strategies you can share.

Thanks!

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u/Basic-Currency2027 — 18 hours ago
▲ 106 r/FPGA

The disconnect between software ai and hardware verification is insane

I am losing my mind watching these tech influencers claim ai is going to replace hardware engineers tomorrow just because an llm managed to spit out a basic 4-bit counter in verilog

they really act like writing teh hdl is the hard part of our job. anyone can write syntax. the actual nightmare is spending 70% of the project lifecycle in verification trying to prove that some obscure edge case won't completely brick a massive fpga. standard probabilistic models just guess the next word based on internet forums. they have absolutely zero concept of clock domain crossing, pipelining, or routing delays

it kinda hit me today while staring at waveforms that this whole autoregressive token-by-token hype is a total dead end for chip design. we don't need a chatbot that guesses syntax, we need systems that actually integrate with formal provers. I was reading up on how some newer architectures like Aleph are pivoting straight into formal mathematical verification instead of just brute-forcing probabilities. Its like finally someone in the ai space realizes that being "99% correct" in hardware just means you manufactured a very expensive piece of silicon trash

until the broader tech industry figures out how to actually prove state machine constraints, i'm just going to keep ignoring the hype cycle and going blind reading timing reports

u/Bos187 — 1 day ago
▲ 1 r/FPGA

Help me identify the PCB

I know it is a Medtronic DANTEC B , 4ch ep ADC Board EMC . I don't know how to use it , I can see it has 3 optical fibres transmitter and 2 receivers .

Is there a manual or datasheet or documents that can help

u/Training-Film-3590 — 19 hours ago
▲ 2 r/FPGA+1 crossposts

Via in pad question

Just sent out my first bga design(.8mm pitch, 3mil spacing) to the board house and received a response that stated I have vias in pad and this service will add 125 dollars to the quote. My vias that are in pad are only for the caps connected to the voltage rails. My research showed that this is typically not considered via in pad because the via is not located on the bga pad, but on the dogbone via. They said I dont have to fill the vias but this increases the risk of shorts and poor soldering quality. So my question is how risky is it to not fill the vias? Not sure if I should just pay for via in pad service or accept the risk if it is low enough for .8mm pitch.

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u/Yorkfire1 — 1 day ago
▲ 35 r/FPGA

x86 Instruction Set Architecture - Tom Shanley

Hi!

By any chance, does somebody have the PDF of x86 Instruction Set Architecture? I have only found books with no more than 200 pages.

u/DisastrousWeight3330 — 1 day ago
▲ 271 r/FPGA+4 crossposts

Free cloud-based VLSI labs that run in one click. No install. No excuse. Do something with your summer.

Every summer I watch people in this field complain about not getting placed, not having experience, not knowing where to start.

So here. Free. Cloud. One click. No setup. No install. No excuse.

VSD has put together free GitHub-based programs for every major area of VLSI and semiconductors. Each one has a cloud lab you open in a browser and start immediately. Build the repo. Show the work. That is what gets you hired.

Physical Design (SoC Design and Planning)

Free: https://github.com/fayizferosh/soc-design-and-planning-nasscom-vsd

Cloud lab: https://github.com/vsdip/vsd-openlane

RISC-V Based MYTH

Free: https://github.com/AnoushkaTripathi/NASSCOM-RISC-V-based-MYTH-program

Cloud lab: https://github.com/vsdip/vsd-riscv2

Semiconductor Packaging

Free: https://github.com/arunkpv/Semiconductor-Packaging

Lab (Windows): https://www.ansys.com/en-in/academic/students/ansys-electronics-desktop-student

CMOS Circuit Design — start here if you are new to this

Free: https://github.com/PRIYANKADEVYADAV15/CMOS-Circuit-Design-Spice-Simulation-using-Sky130nm-technology

Cloud lab: https://github.com/vsdip/vsd-cmos/

RTL Design and Synthesis — also a great starting point

Free: https://github.com/vlsienthusiast00x/RTL_workshop

Cloud lab: https://github.com/vsdip/vsd-rtl

TCL Programming — do this one regardless of where you are in your career

Free: https://github.com/AnoushkaTripathi/VSD_TCL_PROGRAMMING_WORKSHOP/

Cloud lab: https://github.com/vsdip/vsd-tcl

7nm FinFET Design

Free: https://github.com/arunkpv/vsd_asap7_workshop

Cloud lab: https://github.com/vsdip/vsd-7nm

FPGA Fabric Design and Architecture

Free: https://github.com/ShonTaware/FPGA_Design_Fabric_Architecture

Cloud lab: shared during workshop

RISC-V Edge AI

Free: https://github.com/AayusHJainCodely/Risv_Edge_AI

Cloud lab: https://github.com/vsdip/vsd-riscv-edgeai

Analog Bandgap IP Design

Free: https://github.com/chandranshu24-hue/bgr_chandranshu/blob/main/README.md

Cloud lab: https://github.com/vsdip/vsd-bandgap/

All of this is free. All labs run on the cloud. You do not need a beefy machine, you do not need to configure a Linux environment, you do not need to buy anything.

What you do need is to stop waiting and start committing to GitHub.

The semiconductor industry does not care about what you watched on YouTube this summer. It cares about what you built.

u/kunalg123 — 2 days ago
▲ 112 r/FPGA

10 years doing FPGAs and a grey code CDC gotcha got me today

So I've been working on this design for the past six or seven years, and almost 10 years total in FPGAs, and somehow I still ran into something today that I'd never hit before. Figured it's kind of funny in hindsight and worth posting as a case study.

Our design has a lot of clock domains and we're constantly passing signals across them, single bit, multi bit, counters, the whole mix. We try to do things the right way: flip flops where appropriate, double flip flops for single bit synchronizers, handshakes for multi bit, and grey code for counters. Standard stuff.

Today something was glitching out and it was screaming "CDC problem" at me. We had a counter, we were converting it to grey code, and passing it across the domain. On paper, all good.

What I was missing: this counter wasn't running freely up to saturation and rolling over. It was getting reset back to zero somewhere in the middle of its range.

And that's the gotcha. Grey code only works for CDC because consecutive values differ by exactly one bit, so if the receiving domain samples during a transition it either latches the old value or the new value, never garbage. That assumption only holds when the counter increments by one. If you're sitting at 5 (0111 in grey) and you reset to 0 (0000), you've got three bits changing at the "same" time, and the receiver can sample any of the intermediate states.

Grey code on a counter is only safe if the counter is free running or only ever increments by one. The moment something can yank it back to zero, or jump it by more than one step, you've broken the invariant that makes grey code work, and you're right back to the multi-bit CDC problem you thought you'd solved.

The fix in my case was just adding a handshake on the CDC after the grey coding, which works. Though honestly at that point the grey code isn't really doing anything for you anymore, the handshake is what's making it safe. But I left it in because it's not hurting.

Moral of the story is more the gotcha than the fix. Anyone else been burned by this one?

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u/TutorDry3089 — 2 days ago
▲ 439 r/FPGA

LeNet-5 CNN Accelerator Demo

I recently completed a LeNet-5 Convolutional Neural Network (CNN) hardware accelerator designed in synthesizable RTL Verilog/SystemVerilog and implemented on an A7-100T FPGA (xc7a100tcsg324-1). The CNN is trained on the MNIST handwritten digit dataset and optimized for hardware inference, achieving ∼98.2% inference accuracy with uniform Q1.7 fixed-point quantization. The design is implemented as a streaming dataflow architecture to minimize latency.

Here’s a live demo that runs at 100MHz. A python script allows a 28x28 digit frame to be drawn and sent to through the board’s USB-UART bridge. Once the FPGA receives all of the pixels and the TX LED turns off, inference begins and the predicted class displays on the board’s 7-segment display.

u/mjao4 — 2 days ago
▲ 2 r/FPGA

Need Resume Advise

I have applied to hundreds of companies with my resume and most applications are just resume and personal information. I am not hearing anything back, let alone interviews. I know that my past experience is weak but I have been trying to compensate with projects. I am already a Junior and I really need advise on what I could be doing differently. I also link a personal site with all of my projects and additional information. As for the metrics, I can back up each one if asked about it in an interview but I haven't even gotten to that point yet. I am mainly applying for fall and spring CO-OPs as well as a few summer positions. please feel free to be absolutely critical of my resume because I need some unbiased advise.

Edit:

I know my projects are more geared towards software so my current project is a standardized RISC-V embedded processor IP core utilizing a dual capture FSM to orchestrate AMBA AXI4 Lite bus transactions using VHDL · RISC-V ISA · AXI4 Lite · Vivado

u/Emergency-Savings132 — 1 day ago
▲ 17 r/FPGA

Im a lil kid who is new to FPGA

Hi there,

Im a lil kid who is new to FPGA and i Have got two books with me, First is advanced digital design with verilog HDL from 2002 by Mihael Celetti, (i know new version exists but Gemini told me that this book is okay, I got this from my local library) and CMOS VLSI Design by HE Weste and Ayan Banerjee, along with this playlist by Onur Mutlu Lectures 

https://youtube.com/playlist?list=PL5Q2soXY2Zi9Eo29LMgKVcaydS7V1zZW3&si=DMpZ7akPUkPLM84n

Im learning K maps and boolean algebra from the celetti book. im on the right path? should i follow the playlist first or the celetti book first?

u/XoX-o- — 2 days ago
▲ 46 r/FPGA

Is it now waste of money to buy any FPGA board with AMD chip if we are to use free tier of Vivado ?

This recent vivado licence change has just ruined my plans. I ordered a kria kr260 from abroad yesterday, which is supported in free tier Vivado license. However due to the new restrictions on free tier license, I can't stop wondering that if it is waste of money to buy vivado compatible FPGA boards if the user intends to develop on free tier?

My only experience is limited to archaic altera board and I was hoping for transferring that knowledge to vivado ecosystem. But due to this recent development it turns out I need to target an alternative ecosystem, which one do you recommend? Lattice or any other?

Thanks a lot .

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u/evdekiSex — 2 days ago
▲ 11 r/FPGA

Are data structures and algorithms valuable to learn as part of FPGA? Or it’s more suitable to high level software engineering?

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u/Fearless-Can-1634 — 2 days ago
▲ 26 r/FPGA

Built a Real-Time FPGA Anomaly Detection System on ZCU104 Using MobileNet + GRU — Looking for Optimization Advice

My friend and I built a real-time hardware anomaly detection system on an FPGA using a hybrid MobileNet + GRU architecture deployed on a Xilinx Zynq UltraScale+ ZCU104 platform.

The pipeline works like this:

  • MobileNet is used for spatial feature extraction from 224×224 video frames.
  • A GRU processes the temporal sequence information for anomaly detection.
  • The accelerator was implemented on the FPGA fabric, while the quad-core ARM processor on the Zynq handled camera integration and system-level control.
  • We later integrated a 30 FPS camera feed to demonstrate real-time inference.

For testing, since the GRU was trained only on hockey-fight anomaly datasets, we pointed the camera toward a laptop playing YouTube hockey-fight videos to validate the detection pipeline in real time.

Current performance:

  • Input resolution: 224×224
  • Inference latency: ~620 ms per frame
  • Platform: ZCU104 / PYNQ framework

One optimization we already implemented was using a CDMA (memory-mapped DMA) approach instead of a stream-based DMA to reduce unnecessary BRAM/URAM data movement overhead and simplify memory transfers between PS and PL.

I’d really appreciate feedback from the FPGA/embedded AI community on:

  1. Whether this is considered a solid FPGA project for research/industry portfolios.
  2. Suggestions to improve inference latency on the PYNQ/Zynq platform.
  3. Whether moving more preprocessing into PL would help significantly.
  4. Ideas like quantization, pruning, pipelining, double-buffering, AXI-Stream architectures, or using DPU/Vitis AI instead of custom logic.
  5. Whether the MobileNet+GRU architecture is a good fit for FPGA deployment or if there are better temporal models for low-latency anomaly detection.

I’m especially interested in opinions from people who have worked with:

  • AMD Zynq platforms
  • Xilinx ZCU104
  • PYNQ
  • FPGA-based CNN acceleration
  • Video analytics pipelines
  • AXI DMA/CDMA optimization

Does ~620 ms latency sound reasonable for a first custom implementation, or is there likely a major bottleneck in the architecture/design flow that we should investigate

GitHub (other projects): CraftedByDavid GitHub
LinkedIn: David Paul LinkedIn

u/Haza_rd — 2 days ago
▲ 128 r/FPGA

Upcoming Vivado licensing changes.

Seems like 2026.1 will be back to the good old days of licensing.

The no-cost tier is going to be Windows only, with limited simulation and debug features and annual expiry. There is slight carrot in much wider device support at that tier.

But Windows only is a pain... I was so much enjoying native Linux on my non-work laptop. I don't want to go back to Windows+WSL.

u/OnYaBikeMike — 3 days ago
▲ 6 r/FPGA

Should I use value <= 0 or value <='0 in the following code block?

I have the following code block, but I am not sure if I should use value <= 0 or value <='0. What is the difference between the two?

logic [31:0] value, tap;    

always_ff @(posedge clk or negedge rst_n) begin
  if (!rst_n) begin
    value &lt;= '0; // or value &lt;= 0; ?
  end else begin
    value &lt;= value + tap;
  end
end
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u/Just-End6752 — 2 days ago