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r/FPGA

▲ 15 r/FPGA

How do you guys actually handle FPGA constraints? Especially in Vivado

I’m curious how people who work with FPGAs regularly actually go about setting constraints, especially in Vivado.

I’ve been thinking about the constraint-setting workflow and it feels like one of those parts of FPGA development that can get pretty messy pretty quickly, so I wanted to hear how people deal with it in real projects.

A few things I’m especially curious about:

  • How do you usually create your XDC constraints? Do you mostly write them manually, use Vivado’s GUI, start from a board/vendor file, copy from old projects, etc.?
  • At what point in the project do you usually start worrying about constraints?
  • How do you figure out what needs to be constrained in the first place?
  • How do you handle pin assignments, I/O standards, clocks, generated clocks, timing exceptions, false paths, multicycle paths, etc.?
  • How much time do you spend debugging constraint-related problems?
  • What are the most annoying or error-prone parts of the process?
  • Are there situations where Vivado gives you an error/warning but doesn’t make it obvious what you actually need to change?
  • How do you verify that your constraints are actually correct and that you didn’t just get timing to pass accidentally?
  • Do you have any scripts/tools/workflows that make dealing with constraints easier?
  • If you could change anything about how Vivado handles constraints, what would you improve?

I’m especially interested in hearing from people who have worked on larger FPGA projects, where the XDC is more than just assigning a few pins and creating one clock.

Basically, I’d love to know what your real-world constraint workflow looks like, where the biggest pain points are, and what parts you wish were more automated or easier to understand.

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u/Shot-Ad3381 — 20 hours ago
▲ 15 r/FPGA

FPGA Mass Storage

Short and easy.
How do you manage your mass storage on your FPGA system?

Which type of storage and what type of driver?

Thanks

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u/XAX-O-XAX — 1 day ago
▲ 6 r/FPGA

C++ deployer to install ISE 14.7 natively on Windows 11 (no VirtualBox)

Hey sooo im kinda tired of having to either install Linux or Windows 7 on all of my machines to run Xilinx ISE 14.7, or use the VM where there are always problems...

I created a command-line based tool that makes it possible to run ISE 14.7, PlanAhead, and iMPACT directly on Windows 11. And yes, cable drivers seem to work fine as well.

This is bare metal, no VMs are being used. I made it open source, and it really works great for me (im amazed as well lol).

I don't have my Spartan-3 board with me right now to physically plug it in, but since iMPACT doesn't crash or hang and cleanly prints the "cable not found" error, the drivers seem to be staged and working perfectly.

I would really love to get some real-world feedback from the community.

Repo and release are here: https://github.com/GasparisGiorgos/Xilinx-ISE-14.7-Win11-Native

u/ggio07 — 20 hours ago
▲ 3 r/FPGA+1 crossposts

Brand new AMD/Xilinx ZCU104 Evaluation Kits available.

These are genuine, unused ZCU104 boards, ideal for FPGA development, embedded vision, AI acceleration, and Zynq UltraScale+ MPSoC development.

Model: AMD ZCU104 Evaluation Kit
Device: Zynq UltraScale+ MPSoC ZU7EV
Condition: Brand new / unused
Price: $1,300
Original AMD evaluation board
Complete kit

I'm based in India and can arrange shipping. Bengaluru buyers are welcome as well.

If you're interested, DM me

u/Electronic_Bet_5651 — 1 day ago
▲ 2 r/FPGA

DE-10 Lite Board Issues

Currently having an issue with my DE-10 Lite board where it appears my LDRs are stuck in an ‘on’ state such that any code I flash relating to pin the relevant SW and LEDR pin assignments is unresponsive on the board.

I tested a BCD task to test the HEX display and it appears that works fine and I’ve checked my universities universal pin assignment and all is good.

I’ll also not that when I replug the board in for use I DO NOT get a rotating hex display like some of my colleagues, however, the board does respond to being configured and programmed.

I’m wondering if there’s a way I can reset the board? Or ultimately fix this issue?

u/WonderfulHorror1689 — 1 day ago
▲ 7 r/FPGA

I’ve been building a different approach to FPGA development. Would appreciate some technical criticism

I’ve spent the last few months building Forge, a higher-level FPGA development platform, and I’ve just released the first Forge Studio pre-release for Windows and Linux.

The basic idea is that visual design, Rust and Python all feed into the same underlying hardware model and compiler architecture. Studio isn’t intended to be a separate schematic toy sitting beside the “real” workflow.

The current 0.1.0 pre-release focuses on design, validation and simulation. It includes component-based visual design, clocks and CDC, state machines, memories, streaming components, live signal values and waveform viewing.

Hardware Build is deliberately disabled in the public pre-release at the moment because the production target/backend packages aren’t ready to ship yet.

I’m mainly posting here because I’d like criticism from people who actually work with FPGAs.

Things I’m particularly interested in:

  • Where would this approach fall apart on a real design?
  • What would stop you using a higher-level visual/Rust/Python workflow?
  • What FPGA families or boards would actually matter to you?
  • What would Studio need before you’d trust it on a real project?
  • Are there workflows I’m fundamentally overlooking?

Community is free if anyone wants to play with it:

https://forgehw.dev

I’m happy to answer questions about how the architecture works too.

https://preview.redd.it/jbocsqr105kh1.png?width=3440&format=png&auto=webp&s=9e1f8d95b148bcd410132aa866eadf6bc988a811

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u/zacaw99 — 2 days ago
▲ 167 r/FPGA

I got my first fpga

Not much to say I will just use this to flash my existing iverilog hdl projects and write new ones to synthetise to this board.

u/TheAssembler19 — 2 days ago
▲ 37 r/FPGA

Hello,where can I find this book for free:Reconfigurable computing: from fpgas to hardware/software codesign?

I want this book just for some study, to understand better fpga's.

u/david_balaban_09 — 2 days ago
▲ 77 r/FPGA

Finished implementing UART, SPI and I²C from scratch in Verilog

Over the past month, I've been learning serial communication protocols by implementing them in Verilog.

I started with UART, then moved to SPI, and finally finished I²C. I've now put all three into a single repository.

Some of the main features:

  • UART: TX/RX, 16× oversampling, parity and error detection
  • SPI: Master/Slave, all four CPOL/CPHA modes, full-duplex communication
  • I²C: Master/Slave, 7-bit addressing, ACK/NACK, READ/WRITE and multi-byte transfers
  • Parameterized RTL and self-checking verification across the designs.

One thing I found interesting was how different the implementation difficulty was despite all three being serial protocols. UART was relatively straightforward once the sampling logic was sorted out, SPI introduced clock-edge/phase handling, while I²C was easily the most annoying one to debug because both devices share the same bus and SDA has to be released/driven at exactly the right points.

I'd really appreciate feedback on the implementations, verification approach, or anything you'd change to make these closer to practical, reusable communication IP.

(I know many will suggest it is high time to start using SystemVerilog... I promise it's the next thing i am learning lmao)

GitHub: https://github.com/theYash856/Communication_Protocols

Could've posted this earlier, but GitHub decided to go down precisely when I was about to upload the project 😭

u/ThatOrganicArtist — 3 days ago
▲ 20 r/FPGA

Wrote two parallel INT8 MAC engines with 16 bit accumulation on an FPGA with 1120 LUTs and 32 kB BRAM for a diffusion model

Recently I started messing around with the Shrike lite, I wanted to work on a project that was something cool so I started training a diffusion model that generates 32*32 pixel images which could run comfortably on the 256KB of SRAM that the shrike has.

To speed up the calculation I tried writing parallel INT8 MAC engines with 16 bit accumulation, however due to the less amount of RAM it spent a lot of time doing I/O leading it to actually be slower than the MCU only approach (~220 seconds per image vs ~70 seconds per image).

I guess this was expected but it was still fun to tinker around with the microcontroller and the FPGA. A lot of the images look noisy but some actually turned out to be pretty cool.

Full case study here.

edit: added link for case study

u/PandaBean18 — 2 days ago
▲ 23 r/FPGA

LINUX distro suggestion for Analog and Digital electronics softwares ( Vivado, cadence, Siemens etc)

ThinkPad P14s Gen 6, Intel® Core™ Ultra 7 255H Processor
(E-cores up to 4.40 GHz P-cores up to 5.10 GHz), Without operating system, 32GB DDR5-5600MT/s (SODIMM), 1TB SSD M.2 2280 PCIe 4.0 TLC Opal, NVIDIA RTX PRO™ 500 Blackwell Notebook GPU 6GB GDDR7. will be running xilinx fpga softwares(vivado etc), cadance and seimens ( analog and digital softwares).

what linux distro would you suggest

( ALSO: I am new to linux; I am planning to buy this laptop in a couple of months; I want to test distros on my old laptop before I install it on my new laptop; i've just installed ubuntu 22.04 LTS and been tinkering with it and trying to learn linux)

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u/odysseusfromethica — 3 days ago
▲ 0 r/FPGA

OPTIVER FPGA TEST, help needed

https://preview.redd.it/zup97dkiu3kh1.png?width=1218&format=png&auto=webp&s=9f000daebdc7e35b5b3583408bbcdd009af60c92

I recently applied for the Optiver FPGA Internship (2027 Start) and somehow got invited to the online assessment.

Here is the honest truth: I am completely underqualified. My only background is a couple projects, like a UART project, and an stm32 project. Plus, im going into 2nd year, and as a MEng student (4 year course) my "main" internship application year is next year.

However, I want to use this as a reconnaissance mission. I know HFT firms like Optiver have incredibly high technical bars, so I want to take the test just to see what they expect, brain-dump everything afterward, and use it as a study roadmap for when I apply to grad roles next year.

The email states it's a 90-minute proctored HackerRank test (desktop app) consisting of:

  • Multiple-choice questions
  • "Complete the sentence" questions
  • Coding questions

Since I have exactly one week until the deadline, I have a few questions for anyone who has taken this or works in HFT:

  1. What kind of theory shows up on the MCQs? Should I be looking into Clock Domain Crossing (CDC), timing analysis, computer architecture, networking protocols?
  2. What are the typical coding prompts? Are we talking sequence detectors, FIFOs, arbiters, state machines?

I have absolutely nothing to lose here, so any advice on what to look out for during my "recon mission" would be hugely appreciated. Thanks!

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u/izo_dii — 2 days ago
▲ 28 r/FPGA+3 crossposts

Sophisticated Scam. Don't fall for this.

So I was searching for the "RTL Design Engineer" job posting on LinkedIn posts for freshers. I saw a job posting of a SoC Design Engineer for freshers by BareMetal Turnkey Products LLP. This is a registered technical and semiconductor firm based in Bengaluru, India.

I have attached a screenshot of the job post by the person whose work experience section states he is a partner of this company. There was a link to apply, and that was a link to the external website of the company. I applied for the job. Then, next comes the "True value longevity alignment" assessment in the job process. As I started, it turned out to be a soft skill assessment with 134 questions.

And as I completed this assessment and submitted it. Suddenly, I received a call saying this is your interview at 5:34 am! I cut the call. I felt it was a scam.

When I commented about this on the job post, the person who posted this job post accepted that there's a technical glitch in their automated calling system. Then he started gaslighting me and putting the blame on me. I received mail only for the assessment, not for the interview call. This is a breach of professional job process. You don't call for an interview without giving prior notice or mail for it at 5:34 am.

Now, when I opened that page of assessment, it shows my scores, but shows total scores as zero and says I'm low in conscientiousness, openness, etc.

Also, I forgot to mention that this post when I saw was for freshers (0-1) year. It was edited afterwards.

u/notyourwritergal — 3 days ago
▲ 43 r/FPGA

Is FPGA too small of a job market to aim for?

Still in school for an EE degree, I feel like I have a particularly strong draw toward FPGA and RTL design. I even thought about switching to a Computer Engineering major to swap out some core EE courses for things like advanced digital design/computer architecture, and a digital VLSI course, but I thought about it some more and didn't want to be a computer engineering unemployment statistic, and figured having a stronger EE core would be a good floor to have. Too bad, because I really do like this stuff more than anything else so far.

Anyway, am I getting my hopes up by thinking I have a chance at an entry level job after graduating? Is this not really a new grad thing? I plan to make FPGA my main focus in terms of projects. I've read enough to know that they kinda want you to hit the ground running. Mostly interested in defense, communications, networking. I mean, anything FPGA would be great.

Just asking to calibrate my expectations and be aware of the opportunity costs I'd be incurring. Leaning hard into FPGA projects and developing C/C++ fluency (among other skills) means less time spent on the more probable job outcomes.

Thanks for reading.

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u/mushroom_counsel — 4 days ago
▲ 10 r/FPGA+1 crossposts

Do you recognize this FPGA SoM ?

I found this board in my uni's recycling bin. I has a Zynq 7020 FPGA SoC, two Nanya NT5CC64M16GP-D11 RAM chips, and a few other ICs (ethernet PHY, power distribution, EEPROM/FLASH).

It might be a custom board made by someone in our lab (I'll ask around), but in the meantime any information you may have about this SoM is appreciated :D

u/Freddruppel — 3 days ago
▲ 6 r/FPGA

How can I break into the FPGA/digital design industry?

Hi everyone,

I'm an last year Electronics Engineering student from Colombia, close to finishing my degree, and I'd like to build my career around FPGA and digital design.

At university, I learned VHDL and SystemVerilog, working with a Basys 3 and a DE10-Lite. I really enjoyed working with them, and that's actually how I discovered that this is the field I'd like to pursue professionally.

My concern now is figuring out how to actually break into the industry. The FPGA industry in Colombia pretty much Nonexistent, while most opportunities I find are in the US and Europe, and even entry-level positions often seem to require previous experience.

For those already working in the field, I'd really appreciate some advice:

  • What skills should I focus on before applying for FPGA/RTL positions? Are there any courses or certifications that are actually valuable?
  • What kind of FPGA projects would be useful for a portfolio? I'm particularly interested in projects that could demonstrate industry-relevant skills rather than just basic university exercises.
  • Which FPGA development board would you recommend buying? FPGA boards can be quite expensive, especially where I live, so I'd like to invest in something that I can use for several meaningful projects without spending more than necessary.
  • Is a Master's degree necessary or significantly helpful for getting into FPGA/digital design, especially when coming from a country without a semiconductor industry? Or is a bachelor's degree plus a strong portfolio enough to get started?

I'd really appreciate advice from people working in FPGA, RTL/digital design, verification, or related areas.

Thanks!

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u/DelayEducational2689 — 3 days ago
▲ 0 r/FPGA+1 crossposts

register generator suite

Hi, I need a genuine suggestion here. So, I have built a CLI tool that generates SystemVerilog RTL, UVM RAL, C headers, IP-XACT and Documentation from a single JSON register spec -- — with built-in lint and diff. I know already many similar tools exist but my tool has several features which you can't find in open source tool.

**What it does:**

- Takes a register spec (YAML, JSON, IP-XACT, SystemRDL, or Excel)

- Generates 6 outputs in one command: SystemVerilog RTL · UVM RAL · C Header · Markdown Docs · IP-XACT 2014 · SystemRDL 2.0

- **Lint/DRC**: 12 ASIC-focused rules to catch bugs before tape-out (address alignment, field overlaps, reserved gaps, etc.)

- **Diff & Impact**: Compares two spec versions and tells you exactly which RTL, UVM, C headers, and tests are affected — breaking vs non-breaking classified

- **SoC Merge**: Merge 50+ IP blocks into a unified, conflict-free top-level memory map

- **100% offline** — standalone binary, no Node.js, no cloud, air-gap ready

**CI/CD friendly**: lint and diff both return exit code 1 on violations, so you can gate PRs on spec quality.

Community Edition is free (2 registers per block to evaluate). 30-day Pro trial available with no credit card.

Site + download: https://reggen.vlsiworlds.com

Please use it in your projects and give me feedback. Happy to answer questions about the implementation or design decisions!

u/Prestigious_Ant_8060 — 3 days ago