r/FPGA

Horus-Geometry-Fabric

Please have fun: https://github.com/sotiriosc/Horus-Geometry-Fabric

I’ve spent the last few months working on something I call the Horus-Geometry-Fabric. I’m a nobody just learning, and frankly, I started this project with a lot of wrong assumptions. If I’ve managed to accomplish anything useful, it’s a gift—and I’m here to explore, not to argue.

The Context I wanted to see if I could build a better AI hardware primitive. My initial hypothesis was that I could create a "fused" core that would morph between inference (fast/efficient) and gradient accumulation (precise/stable). I thought it would be the holy grail of efficiency.

The Reality Check The silicon told me otherwise. Through a rigorous series of "arenas"—my way of forcing the hardware to prove its own performance—I discovered that fusion is essentially a lie. Trying to force a monolithic datapath to do both jobs carries a massive 1.97× area penalty. It was expensive, bloated, and fundamentally inefficient.

The "Derived" Architecture I stopped trying to "design" my way into a solution and started "deriving" it from the physical constraints the synthesis tools were showing me.

Modularity is the tax: I found that splitting the cores wasn't just about logic—it was about amortizing costs. By refactoring the tile into a lean primitive (~3,188 µm²) and moving the heavy lifting (the normalizer and buffer) to the system level, I got the glue overhead down to 7.2%.
The Float vs. BlockFP debate: I tested everything. I instrumented the "flush" rates in block-floating-point designs, and the data was clear: the standard floating-point paradigm remains "load-bearing" for a reason. You can't beat the efficiency of a per-element exponent without paying a massive area tax elsewhere.

What this is The horus_tile is now a verified, scalable primitive. It’s a dual-core unit—E4M3 for inference and E3M6 for gradients—that actually works. It doesn’t try to be a giant brain; it’s a tiny, efficient piece of math logic that can be tiled across an entire fabric.

The Repository Everything is documented. Every failure, every FAIL verdict, and every measurement that led to the v2 specification is in the docs/ folder.

Closing Thoughts I’m sharing this because I learned a lot by being wrong, and I think the audit trail of these "wrong" turns might be more valuable than the final chip itself. This isn't a finished product; it’s an exploration. I’m just here to see how far the logic goes.

Wishing everyone the best.

u/FarLock9989 — 4 hours ago

▲ 75 r/FPGA

Making a GPU? VGA? : Day 0

Continuation of previous post: "https://www.reddit.com/r/FPGA/s/qQ3FlBdGjT"

Decided to make something like actual display adapter and integrated VDMA to use ps7 ddr3 controller as framebuffer, so now it is essentially primitive 2D Graphics card. Currently set up as single FB device free running.

To demonstrate functioning and justify using full frame buffer via external memory, complemented it with programmable palete LUT buffer (idk why, just to try out pixel stream processing in flight) to convert 8 bit palete color indices from fb to 24 bit rgb and slightly crappy HLS Mandelbrot set ASIC with parallel pipelined engines at 50mhz.

Mandelbrot engine iteration count AXI stream - > VDMA - > Ps7 ddr3 - > VDMA - > palete LUT - > DVI output

Also demonstrated that actual FPGA board (and which one) is in use. CPU is used to initialize ddr3 controller and peripherals and to print Mandelbrot engine status to uart each frame.

Also note that I am not specialist in FPGA yet and just doing stuff I find interesting and trying to learn in process, and this is not Nvidia competitor project ofc.

u/Wide_Jury7005 — 15 hours ago

▲ 10 r/FPGA

Resources for learning FPGA Architecture

I want to learn about FPGAs - their architecture, luts, clbs, their design flow and some development tools. Any good resources for the same?

reddit.com

u/BuySpecialist3474 — 17 hours ago

▲ 6 r/FPGA

Why doesn't the 'Hello World' example application print out its messages on the serial console?

I am having trouble printing out the 'Hello World' print messages on my serial console when I run the 'Hello World' example application on my Zybo Z7-10 board using Vitis Unified IDE 2025.2.

My Vitis workspace

As you can see, both my application and platform projects are built successfully. However I do not see the print messages on the Vitis serial console.

Serial console

I have used UART0 of my Zynq PS in my hardware design and it is reflected in the xparameters.h file:

Zynq PS configuration

XPARAMETERS

I am unable to debug why the application is failing. My questions are as follows:

What value of baud rate should I use? I assume it is 115200 but I get confused by the opening comments in the application which states "This application configures UART 16550 to baud rate 9600. PS7 UART (Zynq) is not initialized by this application, since bootrom/bsp configures it to baud rate 115200". I tried switching to 9600 too but in vain.
Should I use UART1 instead of UART0 and rebuild the bitstream?

Kindly provide the necessary support.

Thanks a lot!

reddit.com

u/RisingPheonix2000 — 13 hours ago

▲ 5 r/FPGA

Need help finding documentation for this specific Alinx AX301 version

Hey everyone, has anyone here worked with this specific version of the Alinx AX301? I can't seem to find any decent documentation for it. This board is based on the Cyclone IV EP4CE6F17C8N chip. Interestingly, it's missing the second 40-pin header; instead, it has a display ribbon cable connector. If any of you happen to have anything saved, could you please share it?

u/whp1611 — 12 hours ago

▲ 6 r/FPGA

Explorer Board Update 2

I have been bringing the Explorer Board up a little more the last few days. The focus of this was to create the System Controller Software.

This is now working with and controlling the PMIC, providing the smart VIO required for the SYGYZY interfaces. It will select the lowest common voltage and set the appropriate PMIC output to the voltage and enable power to the connected SYGYZY pod now. If there is no common voltage or it is above the max 1v8 supported by the FPGA IO then the system will not power the pods for safety.

The system controller also connects into the system monitor (if instantiated) in the FPGA design and reports the junction temp of the FPGA and its voltages. It will also report the system controller temperature also.

So far only a couple of minor things, but we will need to do a short run again to make sure the design is clean and get the board colour correct, before we push for the 3000 production units. these will be at the $99 promised, but future batches might be a little higher.

https://explorerboard.tech/

u/adamt99 — 14 hours ago

▲ 32 r/FPGA

Dedicated AI chatbot for Vivado and FPGA development

Hey everyone,

For anyone currently battling timing closure, deciphering cryptic Vivado error messages, or digging through mountains of AMD/Xilinx datasheets:.

AMD has launched a specialized AI chatbot designed specifically for FPGA and Vivado-related questions and problems.

vivado.amd.com/chat

Has anyone had a chance to put it through its paces yet? I’m curious to see how it handles complex TCL scripting or specific device architecture questions compared to general LLMs.

It also provides a MCP interface if you want to access it over your IDE.

reddit.com

u/BotnicRPM — 20 hours ago

▲ 2 r/FPGA

Guidance needed

Hi everyone,

I'm designing a no-compromise engineering and research workstation intended for long-term use in advanced FPGA, ASIC, AI, and digital twin development. This is more of a research workstation than a desktop PC, and I'd appreciate feedback before finalizing the configuration.

The planned workloads include:
• Very large Vivado synthesis and implementation runs
• ASIC RTL simulation, synthesis, STA, and verification
• FEA simulations
• GPU-based AI model training
• NVIDIA Omniverse and Isaac Sim digital twin environments
• Hardware-in-the-loop testing
• Running multiple engineering tools simultaneously
• Large-scale virtualization
• Continuous software development

The proposed configuration includes:
• AMD Threadripper Pro platform (WRX90)
• NVIDIA RTX 5090
• 256 GB ECC RDIMM memory
• Multiple high-speed NVMe SSDs
• Enterprise-grade PSU
• Workstation-class motherboard

I'm looking for feedback on:
• Whether Threadripper Pro is justified over standard Threadripper for these workloads
• Whether the RTX 5090 is the right GPU or if another option offers better value
• Memory capacity and ECC recommendations
• Storage layout for operating system, active projects, datasets, and backups
• Any workstation reliability considerations I should account for
• Whether there are components that should be upgraded or downgraded
• Overall balance of the build and long-term scalability

If you have experience with workstation-class hardware, EDA tools, HPC systems, AI infrastructure, or enterprise engineering setups, I'd really appreciate your suggestions. I'm aiming for a machine that will remain productive for the next 5–7 years rather than optimizing purely for initial cost.

reddit.com

u/Supremefollower_ — 2 days ago

▲ 13 r/FPGA

need some advices

Hello everyone, next year is my final year as an electrical engineering student, and I'm particularly interested in FPGA technology. There are very few companies in my country working in this field, so I tried to get a summer internship at a French company and made it to the interview stage. Unfortunately, the interview didn't go as I expected. I was asked questions that revealed gaps in my knowledge and I realised that I was doing things wrong. I'm still learning in this field and not yet an expert, and also my low grades had a negative impact on the interview. During the interview, they told me they would contact me by email, but I'm sure they won't accept me for the one-month internship, which is disappointing.
I want to become an FPGA engineer,it's the only field I truly enjoy working in. I'd like to ask how I can develop my skills and get my final internship in this field next year, and ultimately, land a job.
Also, I'd like to ask how I can use AI tools to learn instead of just letting the AI do the work and I just stay watching its work.

reddit.com

u/Brief-Article6459 — 1 day ago

▲ 0 r/FPGA

How do you guys deal with tool chain issues and testing your projects on hardware as you make them ?

Its been a year since i started learning about FPGAs and RTL design in general. I can genuinely say that i have spent 90% of the time fighting tool chains than doing the RTL part. First of all if something works on verilator never in my life has anything worked first try hardware. I genuinely have not been able to get anything more complicated that led blinking or uart to run on my board. I have simple risc v cpus working in simulation but i for the life of me cant get them to work on my board. In order to even test something on the board i need to develop the project to a certain extent and hook up output pins BECAUSE THE FKING IDE OPTIMISES AWAY MY CODE. like if wrote my code it must have been there for some reason right , just compile it bro. If i manage to get it to not optimize away anything , i look under the hood and modules like control units are somehow implemented with just 6 luts. I started with verilator i thought good enough atleast i can figure out the issues , once i get that working , i thought about using open source tool chain. Yosys gave out 15 errors , like if it worked in simulation how can there be new errors in my rtl. I work through them too , then the pnr fails because it thought about optimizing but couldn't so it gave up. Then programmer fails because it cant find the cable , or the port is being used by some random other program. I work through all the tool chain issues only to find that it just doesn't work on my board ? What do i even do at that point how do i find the issue. Another major mistake i think i made was i picked up a gowin board to start. There's like no community , every error i search for either there is no solution or the solution is in some old documentation that they have since updated and is no longer applicable. I even tried their own IDE but even that is a whole box of other issues. I can get it to work on sim , pass through open source tool chain but if i load the same thing on gowin ide , it prints out 7 errors and 50 warnings. I genuinely cant figure out where i am going wrong , i just feel like i am wasting so much time. Recently i made a bare bones structure for a pipelined cpu , it just passes the data through registers , and hooked it to a uart module that does work stand alone. And even that i cant seem to get working, its been 2 days since me just fighting the tools to get something to work on hardware that aldready works in sim.

reddit.com

u/Typhoon__1 — 2 days ago

▲ 4 r/FPGA

I need guidance on why I'm not able to find a starting point in FPGA

I'm an Indian that did Master's in RTU, latvia in adaptronics. I worked as hard as I could and learnt VHDL and FPGA design. I was able to build a thesis on celestial object detection from lunar orbit using Cyclone 10 for a small satellite. I have been applying for internships and starting roles related to FPGAs across Europe but I never hear back or I get rejected without any invitation for an interview. Should I just leave the dream to pursue FPGA? Or is there a way to get entry level role for me?

reddit.com

u/TheBlackFeather_78 — 2 days ago

▲ 0 r/FPGA+1 crossposts

Need some guidance in career path 🙏

I’m a 2nd year ECE student and I’m currently on my 12-week summer break. I’m really trying to use this time to seriously improve my skills and figure out a clear direction in the VLSI/semiconductor field.

Right now I’m learning:

Verilog

ASIC basics

FPGA basics

Digital Design Computer Architecture (DDCA)

In college I’ve done:

Digital Logic Design

Basic Digital Electronics (MOSFETs, BJTs, etc.)

I’m still pretty early in this path, so I had a few questions and would really appreciate any advice from people already working or studying in this area:

What should I focus on next to move toward VLSI/ASIC roles?

What kind of projects actually help for internships at this stage?

Should I focus more on RTL/FPGA projects first, or start learning verification/timing too?

What are realistic internship opportunities for someone in 2nd year?

Any mistakes you made early on that I should avoid?

I’m just trying to build the right foundation and not waste time going in the wrong direction.

Any advice, roadmap, or even personal experience would really mean a lot 🙏

Thanks in advance!

u/yaged3aan — 2 days ago

▲ 2 r/FPGA

Controling every single byte of ram's word independently

For people working on the area:

Sorry for my bad English.

I am building a SoC.

I am studying systems so, before going to college,so I will know pratically everything they will teach.

I am reading books.

I have a dilemma while designing my chip.

1 Is it professional and good to have byte enabling bits instead of just one load bit for all the RAM memory word?

2 Is it professional to have a circuit to arrange the data on the word(mainly with shifts) from and for the ram memory (externally of the ram memory itself)?

The circuit behaviour will be controlled by the control unit.

3 Or would it be better to simply use the last referred circuit to arrange memory, isolating the working bytes and sending the entire word to the ram with only its bits arranged?(I believe you will disagree with this one).

-----------------

This is my first project, but still, I want to do the best choices for mine micro architecture.

-------------

After this project, I will read Quantitive Approach s book by Patterson and Hennessy to learn the trade offs of cost, silicium usage, latency and throughput and power saving.

I thank all the help

reddit.com

u/Rude-Professor-2485 — 2 days ago

▲ 12 r/FPGA

Studying

Hello everyone, I'm an undergrad junior studying stats at an Ivy League. I wanted to ask what do I need to study in graduate school to get into hardware design, for context I'm quant recruiting right now for QT roles.

reddit.com

u/No-Isopod-915 — 2 days ago

▲ 14 r/FPGA

Extra part-time job

Hello guys,

I have been FPGA hobbyist for a long time. Unfortunately, I find extremely hard to motivate myself to work on my pet projects. So I thought that maybe someone is looking for extra help. I can pick up some dull and mundane tasks if this improve my FPGA skills. Also, some compensation would be nice, but this is not a must.

Few words about me - embedded SW engineer with almost 15 years of experience, predominantly in cellular communications and DSP.

reddit.com

u/groman434 — 3 days ago

▲ 0 r/FPGA

Are FPGA Engineers at risk of losing their jobs to AI?

Hey guys , I’m a recent graduate in EEE and I have been writing RTL using VHDL for like a year now but i still consider myself as a beginner. I write my own RTL code and always try to troubleshoot any problems I may face but sometimes I brainstorm with AI if I can’t solve the problems on my own however I never let AI generate my VHDL code.

There is a sentiment that AI will eventually get into FPGA design ( maybe it has already) but I wanted to ask those who are in the industry how much they use AI in their workflow. Will it ever get to a point where AI will be capable to design and implement complex RTL projects without any supervision?

I genuinely enjoy Digital Design but part of me is really anxious about this since the job market has been tough for entry level positions lately. Please if there is any Senior FPGA Engineers I would really appreciate your insight on this.

reddit.com

u/Spiritual-Frame-6791 — 3 days ago

▲ 18 r/FPGA

Online assessment at optiver for fpga engineer what should i prep?

Anyone here had an online assessment for optiver as an fpga engineer?

If yes what should you prep in terms of topics and such

reddit.com

u/LuckyHovercraft719 — 3 days ago

▲ 14 r/FPGA+1 crossposts

FABulous 2.0 released: open-source, silicon-proven eFPGA generator (fabric definition to GDSII)

FABulous is an open-source embedded FPGA (eFPGA) generator. You describe a fabric in a few files, and it produces the RTL, an open CAD flow built on Yosys and nextpnr for compiling user designs onto the fabric, and a tapeout-ready GDSII. It is silicon-proven, with 12+ tapeouts across five process nodes (TSMC 180nm, SkyWater 130nm, IHP SG13G2, GF180MCU, and 28nm CMOS), and supports frame-based partial reconfiguration of individual fabric regions at runtime.

v2.0 is effectively a rewrite since the 1.3 stable version. Main changes:

Full LibreLane GDS flow: generate a tiled, optimised GDSII straight from a fabric definition.
Automatic tile generation from your own primitives, rather than writing tiles by hand.
Run it in the browser: GitHub Codespaces ships the whole toolchain plus the FABulator GUI, zero install, so you can browse/edit a fabric and compile a tile from a browser tab. A Dev Container gives you the same environment locally.
Repackaged as a proper Python package (pip install fabulous-fpga), with a new typer/cmd2 CLI + REPL and a uv-based dev workflow (Python 3.12).
Plus named fabrics, a Nix dev environment (FABulous nix-env) and Docker image, SystemVerilog/.sv handling, blackbox BELs, out-of-tree BEL paths, and a big docs overhaul.

Repo: https://github.com/FPGA-Research/FABulous
Docs and chip gallery: https://fabulous.readthedocs.io/
Release notes: https://github.com/FPGA-Research/FABulous/releases/tag/v2.0.0

Quick start:

pip install fabulous-fpga

FABulous create-project demo

cd demo &amp;&amp; FABulous start

Feedback welcome, especially on the GDS flow and anything that breaks.

u/keeb0113 — 3 days ago

▲ 127 r/FPGA

Making a gpu: Day -1

Decided that gpu pricing is too agregious and decided to make one myself.

Fooling around with mining asic control board (ebaz4205/xc7z020 with HDMI shield), image created by pure logic, no ps7/soft-cpu, no fb: pixels calculation in flight and multiplexing between patterns. DVI 1280 by 720 at 60hz.

Edit: not a serious GPU project, just one-off post because I wanted to share thing I found amusing

u/Wide_Jury7005 — 4 days ago

▲ 54 r/FPGA

AI LLMs will be a critical part of RTL development.

For documentation and logs. That's it, really. I'm never letting it touch consequential RTL in my life. Sorry for the bait.

But seriously, if you haven't tried giving an LLM access to the full documentation of whatever tool you're using, try it. Doubly so if you have an agent. I gave it Questasim documentation and the path to my latest run and I said "this compile crashed, tell me where and why". It was able to tell me the exact line where my coworker flubbed a patch he pushed to the compile script. His runs worked because he had existing libs in the simulation directory, but I was saved an hour of anguish grepping and chasing other errors my testbench was throwing. It's great at telling me all the flags and commands I need for Vivado, adding waves to a waveform window, and some limited success at diagnosing testbench bugs from a csv exported from said waveform. It's way better at grepping than I ever could be. Its tcl is good tool, so if you want a good set of signals to probe, it can give you a good starting position.

reddit.com

u/sincle354 — 5 days ago