u/AnnualMeeting746

Hi everyone,

I am a 3rd-year engineering student working on an 8-bit SAR ADC design in Virtuoso for my project.

Current Setup:

Architecture: SAR ADC with a StrongARM latch + SR latch.

CDAC: 8-bit binary-weighted array

Clock: Running at 10ns

Measurement: Coherent sampling (N=512, M=11) using a rectangular window in the FFT.

The Problem:

My simulated ENOB is hovering around 3.3 bits, and my THD is stuck at approximately 8%...

I have tried a few things like changing the clock frequency..increasing the width of the input transmission gate ..but can't get the THD down ..where can be the problem