r/chipdesign

Hi all,

I've been working on power intent for several years, and kept hitting the same thing: UPF is written by hand, line by line, and the actual power architecture only exists in your head.

It's especially tough for people new to low-power design.

So over the last ~6 months I built Power Intent Studio, an open-source (Apache 2.0) desktop app, with AI as my development partner. You load your RTL and .lib macros, the real elaborated hierarchy appears, and you build the power intent on top of it:

• power domains, supply sets, power switches, isolation, retention, level shifters
• a power state table (exported as a modern power state group or a legacy PST)
• UPF 3.0/3.1 and CPF 2.0/2.1 generation
• loading an existing UPF and mapping it back onto the design; unrecognised syntax is reported with its line number instead of failing

RTL goes through open-source front ends: slang for Verilog/SystemVerilog, GHDL + Yosys for VHDL, liberty-parser for .lib. The repo includes a SystemVerilog SoC example (aura_top) with six domains, three switches and SRAM macros, and its full generated UPF, so you can judge the output yourself.

What it is NOT: a sign-off checker. It doesn't verify that your power intent is correct; it writes what you draw. Structural checks are one of the ideas I'd love to explore next.

I'd really value feedback from people who write UPF every day:

• What would make this useful in your flow?
• Throw your UPF at it. What doesn't load?

Repo: https://github.com/mikespyke17/power-intent-studio

I'm pursuing a Master's in VLSI from a reputable college in India and looking forward to learning SystemVerilog, as it's a key differentiator during the hiring process here. However, I don't know what the future holds for it, and sometimes I am genuinely confused if I'm taking the right path. From what I've observed, entry-level jobs will only decrease while senior-level jobs will increase. How should I proceed? Sometimes it all seems pointless.

I’ve been working with a circuit that can generate both PTAT and CTAT voltages with adjustable slopes through switching.

I’m curious about the possible applications of having variable slope PTAT and CTAT outputs. Apart from conventional temperature sensing, could this kind of circuit be useful in other circuit applications?

I’d really appreciate any ideas or suggestions.

I designed a 16 bit cordic algorithm and verified at both behavioral and Gate level simulation. Would love to hear what you guys think about the design or anything I could improve.

I'm currently looking for a topic for my senior/final-year project.

I'm particularly interested in the intersection of: FPGA / RTL design

wanna learn about Neural Network accelerators and Digital IC / VLSI design

I've been working on vhdl language for a while.FPGA-based digital design, and some embedded systems. I'm also interested in learning more about Verilog/SystemVerilog, ASIC design and AI hardware.

If you were an undergraduate student with access to an FPGA board and basic electronics lab equipment, what kind of project would you choose today in this area?