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r/chipdesign

▲ 80 r/chipdesign+1 crossposts

Analog can Scale. Here’s how.

After the last post introducing the analog/physical computing approach and how by just counting the number of transistors we see how much more efficient it can be, there was a bunch of interesting discussion around how well this could really work. So, I wrote a new article walking through the levels of abstraction from a single transistor to the MNIST benchmark video in the post explaining how an analog computing system would work or scale.

As always, I’m generally happy to answer questions about this stuff :)

u/oddlyspecificndFunny — 11 hours ago
▲ 2 r/chipdesign

Is it sensible?

Is it sensible to professionally focus on chip design in Europe? I'm interested in the technology, but is it gonna left me unemployed? How likely am I to be employed AND build a carreer?

reddit.com
u/ArgsKwargs3131 — 14 hours ago
▲ 16 r/chipdesign+1 crossposts

Switching company @emulation(zebu)

I am attaching my resume, please help me out here.

u/bigboss1358 — 22 hours ago
▲ 239 r/chipdesign

Reddit designed ASIC

A few days ago I reached out on this subreddit for your worst 48 hour ASIC design ideas and you guys did a great job at providing some truly awful suggestions.

In the end I went with thegreatpotatogod's great suggestion of counting until the heat death of the universe.

So I build this design capable of counting for the next 10^(100) years and that broadcast a message over 100Mbps Ethernet with the current count every second.

The design is currently taped out, I am looking forward to getting it back in a few months and making it the new permanent addition to my homelab (until power surge do us part).

For those that are interested, I made a small write-up on it with all the existential dread I could muster: https://talesonthewire.com/projects/until_heat_death_do_us_part/

For those in the US: Happy 4th of July!

u/Ill_Huckleberry_2079 — 1 day ago
▲ 10 r/chipdesign

Moving from the US to Asia. Need help!

Hi, I have been working as a Design Verification Engineer at Apple in California for the past six years, and I am in a situation where I need to make a difficult decision and move somewhere closer to India by the end of this year. I have an approved I-140, so I can return to the U.S. in the future if needed.

I am married and do not have children. The main reason for moving closer to India is my parents' age. I don't want to move to India itself because I have a five-year-old dog who is timid and gets scared even around large or loud dogs at the dog park.

I am considering Singapore or another nearby country with an easy visa process for both us and our parents. A travel time of less than 10 hours to India is also a requirement, as we plan to travel there frequently.

My team at Apple is willing to transfer me to Tokyo, but I would continue working with the same team, which means I would have to work across different time zones.

I am looking for recommendations from people in the same industry. Which dog-friendly country would you choose in my situation as a DV Engineer?

reddit.com
u/love_golden — 1 day ago
▲ 25 r/chipdesign

kepler-formal is now supporting sequential equivalence checking at RTL and gate level

We have updated our open source formal verification tool, kepler-formal, to support full sequential equivalence checking in both RTL and gate level.

What is our goal? An infinite license open source equivalence checking tool that can be used in scale for AI agents and CICD flows and can support industrial grade designs.  

Don't hesitate to reach out to us with issues you found and suggestions you have. We want to hear it!

It will be a long journey to productize a project at this scale, and we acknowledge it, but we are up for the task. 

github.com
u/keplertechioreddit — 1 day ago
▲ 18 r/chipdesign

Seeking advice on careers in mixed-signal IC design

Hi everyone,

I'm about to start an MTech in VLSI after completing my BTech from an IIT. During my bachelor's, I also did a 6-month internship in validation at a semiconductor company. I genuinely enjoyed the experience and learned a lot, but I don't think I'd want to spend my entire career in that kind of role.

What really interests me is mixed-signal design, especially ADCs, and working on challenging R&D problems.

I'm not necessarily dreaming of founding my own startup. I think I'd enjoy being one of the early technical hires in a startup or being on an advanced R&D team inside a larger company.

My questions are:

  1. Do these kinds of roles actually exist in industry, especially in India, or am I idealizing what semiconductor R&D looks like?

  2. For someone who wants to maximize the chances of getting into those roles, is an MTech the right move compared to joining industry immediately after a BTech?

  3. How much of industrial mixed-signal/analog design is genuinely new architecture and research versus product maintenance and incremental improvements?

  4. If you work in one of these roles, what does a typical week actually look like?

  5. Also if you work long term, can you get ownership over some product or IP that you make?

I'm asking because I don't want to spend years chasing an unrealistic picture of the industry. I'd much rather hear from people who are actually doing this work.

Thanks!

reddit.com
u/First_Sandwich5267 — 2 days ago
▲ 0 r/chipdesign+1 crossposts

Need some guidance in career path 🙏

​

I’m a 2nd year ECE student and I’m currently on my 12-week summer break. I’m really trying to use this time to seriously improve my skills and figure out a clear direction in the VLSI/semiconductor field.

Right now I’m learning:

Verilog

ASIC basics

FPGA basics

Digital Design Computer Architecture (DDCA)

In college I’ve done:

Digital Logic Design

Basic Digital Electronics (MOSFETs, BJTs, etc.)

I’m still pretty early in this path, so I had a few questions and would really appreciate any advice from people already working or studying in this area:

What should I focus on next to move toward VLSI/ASIC roles?

What kind of projects actually help for internships at this stage?

Should I focus more on RTL/FPGA projects first, or start learning verification/timing too?

What are realistic internship opportunities for someone in 2nd year?

Any mistakes you made early on that I should avoid?

I’m just trying to build the right foundation and not waste time going in the wrong direction.

Any advice, roadmap, or even personal experience would really mean a lot 🙏

Thanks in advance!

u/yaged3aan — 2 days ago
▲ 5 r/chipdesign+1 crossposts

Struggling with LVS errors (device/net mismatch) on NMOS Cap layout – works fine with MIMCAP. Help?

Hey everyone,

I am working on an IC layout and running into some annoying LVS issues after switching from a MIMCAP to an NMOS capacitor.

When I use a MIMCAP, everything passes LVS without any issues. But as soon as I try to use an NMOS cap instead, the LVS report throws a bunch of device mismatches, net mismatches, and rewiring errors.

I know that MIMCAPs sit high up in the metal stack and are isolated, while NMOS caps sit right in the substrate. I am guessing my issue is coming from how I am handling the bulk connection or how I am tying the terminals together, but I can not seem to spot the exact mistake.

Do I need to explicitly route a guard ring/substrate tap to the Source/Drain metal connection right at the device level? Also, how do you usually structure multi-finger MOSCAPs in the schematic versus the layout to avoid width and length extraction errors?

While using big capacitors and transistors, some times even with maximum limit of length and width of transistors and caps we can't meet the design requirement...does putting multiplier help? or should i have to place one more identical design to meet the requirement (this is particularly in schematics)?

On a related note, I wanted to ask about the design trade-offs here. I know MOSCAPs have much better area density, but it is the voltage-dependent non-linearity of this cap concerns me.

i am using GPDK 90nm i am still in my UG, i don't have access to industry level PDK's as of now. I have used nmoscap_1v from GPDK 90nm, i am trying to do a miller compensated OTA.

Would appreciate any insights or debugging tips on this. Thanks!

u/Ramith_2006 — 2 days ago
▲ 7 r/chipdesign

In Fig 8.7, shouldn't the loop gain be C1/(C1+C2)?

https://preview.redd.it/shykrjb6o1bh1.png?width=885&format=png&auto=webp&s=ead249e4abfd18bf9553b45224fde1f68e5bb40f

https://preview.redd.it/2q94gysoo1bh1.png?width=810&format=png&auto=webp&s=5dbd60e20ed7f06a5287c9bb9d88a13899fbbf2a

He says the loop gain is given by eq 8.8 as it's identical to the CS stage in fig 8.3b (above). But looking at 8.7c, the loop gain looks to be C1/(C1+C2)?

https://preview.redd.it/wepiv9r792bh1.png?width=1227&format=png&auto=webp&s=b42691285f51664904ca740145c95ad30c3be9a1

here is how I tried to solve by breaking the loop (similar to how he breaks it in fig 8.6)

reddit.com
u/maybeimbonkers — 3 days ago
▲ 1 r/chipdesign

Is it possible to transition from an ATE Test Engineer to a Design Verification (DV) Engineer?

I have five years of experience as an ATE Test Engineer and a bachelor's degree in Electrical Engineering. Recently, I've started to feel that my growth in post-silicon ATE test is becoming limited, and I'd like to expand my career into pre-silicon verification. That's how I became interested in DV.

The challenge is that I don't have any hands-on experience with SystemVerilog or UVM.

And.. Since I already have five years of experience as ATE Test Engineer, applying as a new graduate isn't really an option, so I'd have to apply for experienced positions.

Given my background, do you think it's worth applying?

From what I've learned so far, the overall verification methodology in DV feels quite similar to what I do as a Test Engineer. The biggest difference seems to be that DV verifies the design at the RTL level, whereas my current work focuses on silicon-level after fabrication.

I'd really appreciate your thoughts, especially from anyone who has made a similar transition.

reddit.com
u/metamong_zero — 2 days ago
▲ 3 r/chipdesign+1 crossposts

IMPORTANT MUST KNOW TOPICS FOR AMS VERIFICATION INTERVIEW(2-3 YR EXPERIENCE)

Hi everyone,

I have an upcoming interview this Monday for an AMS Verification role at a product-based semiconductor company. I wanted to ask the community what you think are the must-know topics or concepts that I should know before the interview.

Any suggestions, interview experiences, or last-minute tips would be greatly appreciated. Thanks in advance!

reddit.com
u/Perfect_Ad_4164 — 3 days ago
▲ 2 r/chipdesign+1 crossposts

Cpu design teams at Nvidia

Hey folks, need some inputs on the cpu design teams at Nvidia. I currently write RTL for one of the pipeline units. Do the CPU Design teams at Nvidia have good interesting and challenging work and also strong compensation. Would be of great help if people could throw some light on this since GPU is conventionally the flagship product of the company, CPU engine used to be a smaller organization previously. Thanks.

reddit.com
u/Decent-Custard-1747 — 3 days ago
▲ 17 r/chipdesign+1 crossposts

Recived an offer from Birstol UK, what’s your comment on that?11 yrs experience in Semiconductor Industry!

Base:£70,000/-
Bonus:£14,000/-
RSU:30,000/- per annum..
I have 11 yrs of experience?
Did they lowball? Or what is your views?

reddit.com
u/Dangerous_Crow8566 — 5 days ago
▲ 26 r/chipdesign+1 crossposts

What Physical Design projects will actually help me stand out from the crowd?

Hi everyone,

I'm an entry-level VLSI Physical Design engineer trying to build a portfolio that will make my resume stand out for product companies (NVIDIA, AMD, Qualcomm, Apple, Intel, Synopsys, etc.).

I don't want to do only the common OpenLane or basic RISC-V implementation projects that everyone has. I'm looking for projects that demonstrate real Physical Design skills and engineering thinking.

What projects would you recommend that recruiters and hiring managers actually find impressive?

Specifically, I'm interested in projects involving:

  • Floorplanning
  • Power planning
  • Placement and CTS optimization
  • Routing and congestion analysis
  • Timing closure
  • IR drop and power optimization
  • Physical verification (DRC/LVS)
  • Automation using TCL or Python
  • OpenROAD/OpenLane or any industry-relevant open-source flow

I'm willing to spend several months on one high-quality project if it significantly strengthens my resume.

If you were hiring a junior Physical Design engineer, what project would immediately catch your attention and make you think, "This candidate is different"?

I'd really appreciate suggestions from engineers working in the semiconductor industry. Thanks!

reddit.com
u/SathwikVenkateshRao — 4 days ago
▲ 8 r/chipdesign+4 crossposts

Dec 2025 MS CE grad looking for New Grad DV / Embedded / Firmware roles in USA

Hi everyone,

I don’t usually post like this, but I’m honestly in a tough situation and trying my best to find a new grad opportunity in the U.S.

I graduated in Dec 2025 with an MS in Computer Engineering from a public university in the Bay Area, with a 3.83 GPA. My main focus was computer architecture, embedded systems, microprocessor design, advanced computer design, and hardware/software integration.

I’m looking for new grad / entry-level roles in Design Verification, Validation, Embedded Software, Firmware, Systems/Platform Software, or SoC-related roles.

My skills include C, C++, Python, embedded C, Verilog/SystemVerilog basics, FPGA/Vivado, Linux debugging, scripting, memory-mapped register validation, and hardware/software debugging.

I have 6 months of software engineering internship experience and also worked as a TA/Instructional Student Assistant for multiple computer engineering courses, where I helped students with labs, debugging, and grading.

I did get good interview opportunities with companies like Amazon Annapurna, NVIDIA, ARM, and Qualcomm, but due to headcount/timing/final-round outcomes, nothing converted. I’m still preparing seriously and I’m interview-ready. I can do Blind 75 / LeetCode 150-style coding interviews and can interview remote or onsite.

I’m authorized to work in the U.S. and open to relocate.

If anyone knows any recruiter, hiring manager, referral, or opening for DV / validation / embedded / firmware / systems roles, please let me know. I would genuinely be grateful for any help.

Resume available on request. Thank you for reading.

reddit.com
u/Reasonable_Ninja7106 — 3 days ago
▲ 46 r/chipdesign

My brain is fried: give me your worst 48 hours ASIC design ideas

Do your worst, this is a serious request.

Update: I am going to go for a mix between the thegreatpotatogods and No_Crow8317s idea and design a counter that has enough bits to count until the heat death of the universe (technically also a random number generator). Also I will be making it return the counter value wrapped in an Ethernet frame every second because I don't have time for validating any firmware (and I like Ethernet).

Proof I am actually building it:

https://github.com/Essenceia/Until_Heat_Death_Do_Us_Part

u/Ill_Huckleberry_2079 — 5 days ago
▲ 46 r/chipdesign

8 bit SAR ADC

Hi everyone,

I am a 3rd-year engineering student working on an 8-bit SAR ADC design in Virtuoso for my project.

Current Setup:

Architecture: SAR ADC with a StrongARM latch + SR latch.

CDAC: 8-bit binary-weighted array

Clock: Running at 10ns

Measurement: Coherent sampling (N=512, M=11) using a rectangular window in the FFT.

The Problem:

My simulated ENOB is hovering around 3.3 bits, and my THD is stuck at approximately 8%...

I have tried a few things like changing the clock frequency..increasing the width of the input transmission gate ..but can't get the THD down ..where can be the problem

u/AnnualMeeting746 — 5 days ago
▲ 62 r/chipdesign+4 crossposts

What is the right roadmap to learn semiconductor design without getting lost?

A lot of students want to enter semiconductor design, but many get confused about where to start.

Some jump directly into physical design.
Some start with RTL.
Some try analog first.
Some only watch videos and collect certificates.

In my opinion, a beginner-friendly roadmap should look something like this:

  1. CMOS Understand transistors, basic circuits, SPICE simulation, and how devices behave.
  2. RTL Learn Verilog, digital logic design, testbenches, and simulation.
  3. Physical Design Understand synthesis, floorplanning, placement, CTS, routing, timing, and how RTL becomes layout.
  4. Physical Verification Learn DRC, LVS, antenna checks, density, PEX, and what it means to make a design tapeout-ready.

For someone who already knows RTL and basic physical design, jumping directly into an internship-style physical design project may make more sense than restarting from zero.

The bigger point is this:

Interest in semiconductors is not enough anymore. Students need proof — GitHub work, simulation results, reports, screenshots, debug notes, and projects they can explain.

Curious to hear from people already working in VLSI / semiconductors:

Would you change this order?
Should beginners start with CMOS first, or RTL first?
What would you tell a student who wants to enter chip design seriously in 2026?

u/kunalg123 — 5 days ago