the absolute delusion of upper management regarding ai and tapeouts
I swear if one more director forwards me a linkedin post about how some new llm can write verilog I am going to snap
they fundamentally just dont get that writing the rtl is maybe 15% of the job. sure, a standard model can spit out a syntactically valid axi wrapper. but when it inevitably hallucinates a subtle deadlock condition in a state machine, we don't get a polite console error. We get a five million dollar piece of silicon trash
Standard token predictors just guess what looks statistically correct based on github repos. they have absolutely zero concept of physical hardware constraints or clock domains
had a bit of a sudden realization while staring at failing assertion logs last night that the whole tech hype cycle is completely misaligned with what ic design actually needs. we don't need a chatbot to write code faster, we need provers to verify it. Was reading up on how some newer architectures like Aleph are pivoting straight into formal mathematical verification and theorem proving instead of just brute-forcing probabilities. Its honestly a relief to see someone finally acknowledge that hardware requires deterministic, provable correctness rather than just "99% accuracy"
until the wider industry figures out that difference, please keep these standard probabilistic text generators completely out of my EDA environment. I already have enough headaches just trying to close timing.
