u/Lazy-Astronomer8932

I'd love to hear from r/chipdesign about the biggest problems/oppurtunities in your jobs/broader industry. Can be literally anything, from EDA to design or some random idea you think might be interesting to explore. I’m hoping this can turn into a useful thread where we can combine industry experiences, and people dump observations, annoyances, and ideas.

Context:

• I'm a final year ECE student. I'm joining ARM soon as a grad, but I'd really love to pursue something hardware related as my own idea. I've had a few internships around uarch, asic design + 1 actual tapeout as part of a uni module.
• Not trying to be the next Cerebras per se, and lots of ideas generally require huge amounts of capital and exptertise. Given increasing focus on chips for AI inference & training, I'm really hoping there's something niche but integral that I can contribute to.
• Recently posted asking about problems with EDA tools taking ages, got some fantastic replies
• It's hard as a student to validate ideas to problems you don't even know exist without having worked in the industry. I really just want to hear about people's daily issues in this space.
• Please just comment any ideas or thoughts you've had!! I'm sure others have had them as well and they can upvote 😄

Hi, I’m a student looking into bottlenecks in EDA workflows. I’ve done a few small FPGA projects in both Quartus and Vivado, and even for small designs I found synthesis and place-and-route could easily take 10–15 minutes.

This year I also had the chance to tape out a small accelerator on a 40nm process through my university. In that flow, full PnR runs often had to be left overnight, which made me curious about what timelines look like in industry for larger and more complex designs.

For people working in ASIC or FPGA design professionally:

• How long do synthesis, placement, CTS, routing etc. typically take for your designs?
• Roughly how large are the blocks you work on (standard-cell count, macros, area, process node, etc.)?
• How much time is usually allocated for physical design within a project schedule?
• How many PnR iterations are typical before timing/power/area targets are met?
• Can you control the underlying placement/routing strategies and optimization algorithms or are the EDA tools fairly black box?

I’d be especially interested in hearing about experiences from modern advanced nodes as well as FPGA workflows at scale.