AXI-4 Lite VIP by myself?
Hi all,
I am a grad student trying to equip myself with a decent amount of knowledge in verification. I figure it is better to actually work on a project than to just learn SystemVerilog directly.
Is verifying an AXI Lite (slave) doable over the summer (~2 months)? Also, is it even a good starting point for verification? The reason for this question is that I have heard that even AXI Lite's complexity is a lot to verify (corner cases and such). Also, to be specific, I'm not targeting formal verification. Also, I am not sure if I can attain 100% coverage - I aim to have it as close to 100% as possible.
My background: I have a decent amount of RTL skill, but not as much in verification. I have, however, worked on verifying a processor as part of a course, and I know how to write simple testbenches, including covergroups, and attain full coverage. I just want to clarify whether this DUT is something I should pursue, as I am not sure whether it is too complex.
I will first work on an asynchronous FIFO to become comfortable with advanced SystemVerilog and UVM, and then port it to AXI Lite. I have previously worked on TileLink-UL (the open-source parallel to AXI Lite), so I feel I can carry that knowledge over.
Edit: I was going to use ZipCPU's AXI-Lite DUT.