
What's up with this bias voltage generation for cascodes?
(Edit: schematic shown is a simplified version of Fig. 18 in this paper.)
Today I ran into the circuit below for biasing cascodes, which I never saw before. What would be the advantage(s) of generating the cascode bias voltages (Vcp, Vcn) in this way? (I mean, compared to classic approaches like the ones in this post)?
Since in the circuit below the generation is achieved through both NMOS and PMOS diodes, is it perhaps better across corners due to some weird NMOS/PMOS cancellation effect?
Thanks in advance for any ideas!
P.S. Or if anyone knows an early reference proposing this type of biasing, that would also be great!