▲ 4 r/FPGA
FIR IP in Quartus configured for Interpolation
Why does my Altera FIR IP, configured for interpolation by 80, produce the expected outputs when I provide 3 input samples, but fail to produce the expected behavior when I provide 10 input samples? In this case, the FIR IP keeps tready asserted high, but only generates 4 valid outputs. What could be causing this behavior? I am simulating this in Quartus Prime Lite Edition.
u/BackEmergency2317 — 1 day ago