Zybo Z-7010 SoC frustration
got ahold of a Zybo Z7-10 from uni around a week ago and this is my first proper SoC FPGA experience. ive used normal FPGA before but this zynq PS side has genuinely been driving me insane
all i wanted to do was get a basic UART hello world running through Vitis 2025.2 over JTAG and i still cant get consistent UART output from my own application
in QSPI boot mode i can at least see U-Boot/boot logs on serial terminal, but my own app outputs basically nothing
things ive already tried/debugged in order:
enabled UART1 + verified MIO48/49 mapping
result: UART config in BSP/xparameters looked correct
tried normal hello world with xil_printf/print/printf
result: absolutely no UART output
tried different baud rates + serial terminals
result: mostly blank terminal
used XSDB manually to download/run ELF
result: ELF downloaded successfully but still no UART output
set breakpoints at main()
result: main() breakpoint hit successfully so application was at least starting
checked DDR through XSDB
result: got "Cannot access DDR: the controller is held in reset"
kept getting vector catches at 0x0
result: looked like runtime crashing very early
debugged FSBL behavior
result: FSBL entered fallback loop at one point
got hw_server conflicts + repeated xsdb weirdness
result: constantly restarting/debugging sessions
got DAP IDCODE failures + usb bulk read failed + ftdi_write_data_submit failed
result: debugger/FTDI communication itself started looking unstable
- ttyUSB disconnect/reconnect spam in dmesg
result: FTDI interfaces repeatedly disconnecting from USB
- manually tested DDR reads/writes later after rebuilding platform/preset
result: DDR eventually became readable and system looked more stable
- later vector catches reduced and CPU started stopping at 0x8 and 0xC instead
result: execution looked more stable than before
- tried direct XUartPs driver + raw UART register writes
result: still no proper UART output
- changed linker/memory setup away from DDR and used memory_ram/OCM instead
result: RX LED finally started blinking and terminal showed gibberish instead of staying completely blank
the weird part is that pure FPGA/PL stuff works completely fine. i made a simple pushbutton -> LED design and it worked instantly first try, so the FPGA fabric itself seems healthy
i genuinely dont know what im missing anymore because this is my first time working with a SoC FPGA and almost every tutorial online is for older Vivado/Vitis versions where the entire flow looks different
at this point i cant even tell whether the actual issue is:
DDR init
FSBL handoff
UART/stdout routing
debugger corruption
FTDI/USB instability
or just me misunderstanding zynq bringup entirely
is this normal zynq beginner pain or am i missing something obvious here
would seriously appreciate guidance/resources from people using newer Vivado/Vitis versions