I set significantly lower frequencies for ccd1 on my ryzen 9900X to accommodate for the lower undervolt which is -45 all the way to -55 depending on the cores frequency. On ccd0 I have -25 all core with no stretching. Also, I have CO guard turned on on a 0 curve to prevent any idle crashes. Any opinions? All are welcome and im happy to learn
I see many posts on this r/overclocking with people running 6400-6600MT/s but then they have 65000MB/s READ, do they have bad signal integrity and lose 25000MB/s? Or why do I get 90000MB/s on 6000?
Is there anything else I can do? Im currently at a moderate 1.45vddq with 0 errors after 5hrs on occt Als my FCLK is 2200mhz SOC 1.25V VDDIO 1.33V Misc 1.1V Cant get lower TFaw cuz my imc just wont handle it even 20 with trrdL on 4
All pins are perfect, has a 2 year warranty. And a brand new board from a trusted partner is 780€ Wasnt used for sub-zero only custom loop Need it for 6600 cl26/28