▲ 1 r/FPGA
How are you handling >200% SLR utilization in Vitis HLS?
on alveo U250 (vitis 2022.1), i have a kernel that calls the same function 7 times per layer with different output sizes. HLS kept duplicating the hardware (5 engines, 200% SLR LUTs) because each call connects to different m_axi ports. ALLOCATION limit=1 did nothing, i also tried other tricks still nothing.
I fixed it by writing all outputs to a single float workspace[FFN] array, then copying to the real destination. Now HLS sees identical function signatures and finally builds only 2 engines (LUTs 77% of SLR). Routing still heavy but at least fits.
Is this a known pattern? Any cleaner way to force sharing across calls with different memory interfaces? Or do you just go multi‑CU after 70%?
u/Dazzling-Duck-4437 — 8 days ago