u/EdgeSad7756

I have spent some time looking into this and have not seen this approach mentioned anywhere. Assuming the data_in is mostly static relative to the clock frequencies and that the data_out updates are not clock-cycle-critical, is this a valid metastability approach, or am I missing something?

reg [7:0] data_r1,data_r2,data_r3,data_out;

always_ff (posedge clk_b) begin
  data_r1 <= data_in; // 8 bits from clk_a domain
  data_r2 <= data_r1;
  data_r3 <= data_r2;
  if (data_r3 == data_r2) 
    data_out <= data_r3;
end