u/Elipsem

https://preview.redd.it/py4piuezbm2h1.png?width=1919&format=png&auto=webp&s=1605538be5e06662a9c1245f696c7649c3479437

I have the graph set to be the output voltage. Also some things I did was I set the fall and rise times to about .01ps because when I set it to 0, LTspice automatically changes it to have some fall time. This was bad for my design because both transistors can't be on at the same time.

The thing that is bugging me is that the output is only .6 volts, but because I have a 50% duty cycle I thought the output should be half of 10 (5V). Also when you zoom in on the output waveform it is a triangle wave modulated by a sine wave

Hello, I am trying to work on modeling different transistor circuits in LTSpice starting with super basic ones like this and working up to more advanced circuits like an operational amplifier or something. But before I do that, I need to figure out why this simulation is giving weird results.

Simple DC transistor circuit. Nmos on top and Pmos on bottom

The current is what is tripping me up because it looks like the bottom transistor is on when really the top transistor should be on. I am just getting started modeling transistors in this software so I am not sure where to look to solve this issue. Any advice greatly appreciated