![Image 1 — [Review Request] DDR Ram Routing](https://preview.redd.it/3tkbw6p15l1h1.png?width=1016&format=png&auto=webp&s=be292b7de5805d7e2bd69d3cc61dc57b2a8d80af)
![Image 2 — [Review Request] DDR Ram Routing](https://preview.redd.it/rwpzo3p15l1h1.png?width=701&format=png&auto=webp&s=ec8ab6aa1a3a14f64783f34adfc065a3fa17f5e1)
![Image 3 — [Review Request] DDR Ram Routing](https://preview.redd.it/562se4p15l1h1.png?width=990&format=png&auto=webp&s=0225f753050e32406ad3ad4a1a8b6c18b958e72f)
![Image 4 — [Review Request] DDR Ram Routing](https://preview.redd.it/oevre5p15l1h1.png?width=710&format=png&auto=webp&s=9aa25089e3619ebe7c3d9cd71e94965fb87d74f1)
[Review Request] DDR Ram Routing
Hello!
I'm mostly finished with this DDR routing for the Allwinner A33. I'm only done and wanted to ask some questions.
The stackup is as follows:
L1-SIG
L2-GND
L3-PWR
L4-SIG
L5-GND
L6-SIG
A few questions I have are:
What's the simplest way to make a reference voltage for the VREFCA and VREFDQ pins on the DRAM chip?
Do I need extra components on the CK/CK# lines?
Will the signals on L4 be badly interfered with by the power islands on L3?
Will crosstalk be a large problem with the long parallel traces?
Thanks!