u/Important-Ad5990

I have a rather unusual requirement and I can't find any off-the-shelf part or design procedure to implement it. I need a simple zero-pole, high shelf filter that'll have constant attenuation between DC and say 1GHz, then 3dB slope between 1GHz and 3Ghz, I don't care what happens afterwards. I also care about phase response as this system will be transmitting sharp pulses that I'd like to see undistorted. It's meant to compensate for limited bandwidth of final stage of my RF chain.

I tried designing with 2 diplexers and attenuation in low frequency arm but I couldn't find any DC coupled diplexers that can work up to GHz. I also looked into various equalizer designs and parts but they seems to insist on having a slope from their low frequency limit and not a flat response up to some f1 and slope between f1 and f2. Does anyone know how to design such a filter?

Before anyone asks it's needed for a research project regarding pulsed laser diodes. Most diodes have package inductance of around 5nH, which, when driven with series 50R, limits bandwidth to about 1GHz. I'd like to place this filter before final power amplifier (QPD1010) to generate an overshoot, that'll increase an effective bandwidth.

Hi,

on my quest to make a discrete microcontroller that can compete with avr family I stumbled on ken sherrif's blog post on arm1 and how it sends one of ALU ports always through a barrel shifter. I decided that it's a genius idea, now I just needed to design a barrel shifter. A barrel shifter is essentially a set of prewired muxes that select every output from N+1 inputs (all input bits and 0 or sign extension). The classical 74F153 and 74F157 are just much too slow for that (7.7ns typical and I need to stack 2 at least) so I decided to build it from transmission gates.

The design consists of 5 rows of 2:1 muxes (74LVC1G3157), working as shift or bypass by specific power of 2 (>>1, >>2, >>4, >>8 and <<16). It turns out that the ordering of muxes changes how many are needed in total with >>2, >>4, <<16, >>8 and >>1 requiring "just" 98 mux ICs.

Every mux provides 18pF of load capacitance, 5 of the stacked give 100pF of load for every input data pin. It's not the best but survivable, that is unless one enables sign extension. Worst case sign extension copies highest bit to all output bit, loading it with 1.6nF in total, which is just a bit too much. In the end it turned out that the simplest way is to send MSB through 4 AND gates that both buffer the signal and enable sign extension. Ironically the 74F08 has typical propagation delay of 4ns in 50pF, while the entire series of TGs has a delay of just 3.6ns.

the barrel shifter PCB

PS

A few explanations above are incorrect but I wanted to simplify as much as possible for the sake of clarity:

• The circuit can be simplified to use just 97 muxes, but I wanted >>8 to be as far as possible to minimize loading on sign extension gates.
• The muxes have 7.5ns propagation delay from control signal, but it arrives before data (control signal is from a flip flop, while data comes from flip flop that has it's OE toggled by another flip flop adding about 4-5ns to the path).
• There are 74LS244 buffers at the output just for visualization. They can be disabled with a jumper or my removing the ICs if 4pF of input capacitance becomes a problem.

Hi everyone,

I'm trying to learn how to optimize my high speed PCBs (think <100ps edges), especially focusing on SMA transitions, vias and power combiners. I've got a brick wall trying to hand tune stuff by trial and error and would like to move to simulation based optimisation.

I did some research into free/cheap FEA simulators and it seems that openEMS is the most recommended one. Unfortunately all the materials I found do a terrible job at explaining how to use it. Does anyone have any good source to recommend?