I just downloaded it today and it seems like a pretty great implementation of what its going for....

(that being to allow you to model your geometry in FreeCAD, set up your ports and mesh entirely through the FreeCAD GUI, and solve for your EM results you want)

After playing around with scripting for OpenEMS and being a little disheartened with how cumbersome it is as an HFSS user seeking a Free Open Source alternative for hobby projects it honestly seems like an ideal solution.

Apparently it only dropped like 3 weeks ago as well!

Anyone else checked it out?

It uses a ton of different solvers to do different tasks....Palace, OpenEMS, a few others....

The GitHub page descriptions are written by Claude....seems a bit strange but cant really write it off just because of that..found some forums and people seem to have gotten real results....will do some of my own tonight

Edit: found this forum post

https://forum.freecad.org/viewtopic.php?style=2&p=900323

Which has some discussion but it links to a "website" of the creator which is entirely AI generated slop.......so this makes me a bit distrustful.......try it yourself and see if any of it works

Hey everyone, ECE student here. hope you're well.

I'm conceiving a device that detects rf, caracterises protocols mac addresses etc. I chose to go with dongles to connect to my mircroprocessor so it can be easier to decode and handle signals + modularity. I had a question rgarding the numbers of dongles. If i take wifi for example, is it better to put multiple dongles if im working in a noisy rf environment? is the number of dongles important for processing information smoothly? the goal being to lose minimum data.

The setup: two identical parallel half-wave dipoles (300 MHz, 0.477 m, 0.5 mm wire radius, 21 segments each in NEC2), spaced λ/4 apart. The textbook cardioid recipe says: feed the second element a quarter cycle behind the first — currents (1∠0°, 1∠−90°) — and the pair forms a cardioid with the null off the back.

The obvious first move — and a very common one — is to hand those phasors to the SOURCES: equal voltages, 90° apart. The θ=90° azimuth cut of that run: front-to-back 3.4 dB. Not 30 — three point four.

https://preview.redd.it/xpxb7qqmmbkh1.png?width=782&format=png&auto=webp&s=c4fe4f7772b0124dfb7ad028230211537623e2b5

The reason is that the two feed-points are nowhere near independent. Measuring the mutual impedance of the pair (drive each port at 1 V in turn, the un-driven port left as plain continuous wire = shorted; read both feed currents, invert the Y-matrix) gives, at λ/4 spacing:

Z11 = 70.15 − j1.27 Ω      Z12 = 37.25 − j31.64 Ω

|Z12| ≈ 48.9 Ω against |Z11| ≈ 70.2 Ω — the coupling term is about 70 % of the self term. A voltage applied at one port drives current in BOTH elements, so setting port voltages does not set element currents, and the pattern is made of currents.

The fix is two lines of algebra. Decide the currents you want, then feed the voltages the coupled pair actually needs — V = Z·I:

V1 = Z11·(1∠0°) + Z12·(1∠−90°) = 54.5 V ∠ −45.0°
V2 = Z12·(1∠0°) + Z11·(1∠−90°) = 108.0 V ∠ −70.5°

A 2:1 amplitude ratio and only 25.5° of phase offset — nothing like the recipe phasors. Feed exactly that, same wires, same solver: front-to-back 29.6 dB, and the achieved feed currents match the target to one part in 10⁴.

https://preview.redd.it/xl8wkmgxmbkh1.png?width=782&format=png&auto=webp&s=66fe22f871c2e0bf7208013dc135735baf1a82e5

(Both polar plots use the same fixed −40…0 dB radial scale, so the two patterns are directly comparable.)

Nothing changes between the two runs except the drive. That is the whole point: the recipe was never wrong, it was a statement about CURRENTS, and a voltage source doesn't deliver it.

Disclosure: these numbers came from EMStudio, a FreeCAD workbench I build — that's my interest here. Happy to answer questions either way.

Hi

I would like to design a wideband balun from 0.5-12GHz on MMIC.

Can you suggest some ideas/reference to start with? I'm not sure if a Marchand Balun would be able to cover this much bandwidth.

Thanks

I am looking for practical engineering perspectives on something I keep seeing in outdoor electronics, enclosures and reliability screening:

Many environmental assessments still describe a deployment location with average temperature, annual precipitation or a broad climate zone. But for electronics reliability, those numbers often feel too indirect.

From a reliability point of view, the more relevant questions seem to be:

- How many hours per year does the product see RH > 80% or RH > 90%?

- How often does air temperature approach the dew point?

- Are there repeated condensation-prone periods?

- Is the site exposed to marine chloride or industrial sulfate background?

- How much thermal cycling occurs over typical daily and seasonal operation?

For example, two sites can have similar average climate conditions but very different moisture exposure profiles. One may have frequent night-time dew-point convergence, while another is hot and dry with much stronger thermal cycling.

I am curious how other engineers handle this in practice:

1. Do you use hourly climate data, design days, test standards, field experience or something else?
2. Do you explicitly evaluate RH duration or condensation potential?
3. For connectors, PCBs, coatings or outdoor enclosures, what environmental metric has been most useful in real design reviews?
4. Are there failure modes where traditional climate classifications were misleading?

I am especially interested in non-confidential examples from electronics, outdoor power electronics, HVAC, solar, BESS or automotive ECUs.

Hopefully focusing on that hardware design but i also want to know the physics and DSP stuff

I'm a senior Electrical Engineering student graduating soon with a 3.6–3.7 GPA. I'm a U.S. citizen and I'm interested in RF/communications/telecommunications, particularly in defense or aerospace.

I don't have an RF/telecommunications internship or significant personal projects specifically in the field. I'm trying to figure out how realistic it is for me to get an entry-level RF/communications engineering position after graduation.

I'm considering companies like L3Harris, RTX/Raytheon, Northrop Grumman, Lockheed Martin, Boeing, General Dynamics, etc.

Would my GPA and EE degree be enough to realistically get interviews if I apply broadly, or am I at a significant disadvantage without internships/projects?

Also, for those who have interviewed for entry-level RF/communications/defense engineering positions:

• What technical questions were you asked?
• What EE/RF topics should a new graduate know well?
• Did they ask about things like S-parameters, Smith charts, transmission lines, link budgets, filters, amplifiers, antennas, DSP, etc.?
• How much of the interview was technical versus behavioral?
• Did they ask you to solve problems on a whiteboard?
• How heavily did they question projects or coursework on your resume?
• What questions did you wish you had prepared for?

What would you recommend I learn or build during my remaining senior year to become a stronger candidate?

I'd especially appreciate answers from people who currently work in RF/communications or defense and who have experience interviewing/hiring new graduates.

I'm working with a 3 stage amplifier circuit with multiple splitter/combiners on the final stage. The signal after the first two pre-drivers is split once for two power modes. Each power mode is split again to a pair of amps to be recombined, then combined once more to have all final drivers in high power mode. This ends up with a total of 4 final drivers with 6 90° shifts from all the splitter/combiners.

With each trace (4 total) are tunable capacitor options. By default they all have the same values. The issue at hand is that by the final combination there is a singal large (2-3dB) dip from destructive interference only on the full power mode. My question is, to tune this out should I approach making cap tuning changes in pairs, one trace at a time, asymmetrical in size or direction, or even just one cap at a time? When only 2 of the four final drivers are on, the power band is quite flat. When the last pair are added, the problem surfaces. Should I focus on just one pair of traces, or change one trace on each pair?

Any advice appreciated.

Hi everyone,
I’m looking for a small, affordable radar module for a research project.
Requirements:
Operation frequency 24 GHz (or less frequency) FMCW
At least 1 TX / 2 RX
Preferably I/Q data from both RX channels

On-board ADC with access to raw ADC/IQ samples
USB/SPI/UART output preferred
I want to do my own range, Doppler, AoA and micro-Doppler processing, not just receive processed target data
Budget: Maximum $250

I’ve considered the RFbeam K-LC7, which has 1 TX / 2 RX and analog I/Q outputs, but it requires an external ADC.
I’m looking for something similar but with the ADC already integrated.

Should I go with RFbeam K-LC7 and buy external ADC board?

I have a rather unusual requirement and I can't find any off-the-shelf part or design procedure to implement it. I need a simple zero-pole, high shelf filter that'll have constant attenuation between DC and say 1GHz, then 3dB slope between 1GHz and 3Ghz, I don't care what happens afterwards. I also care about phase response as this system will be transmitting sharp pulses that I'd like to see undistorted. It's meant to compensate for limited bandwidth of final stage of my RF chain.

I tried designing with 2 diplexers and attenuation in low frequency arm but I couldn't find any DC coupled diplexers that can work up to GHz. I also looked into various equalizer designs and parts but they seems to insist on having a slope from their low frequency limit and not a flat response up to some f1 and slope between f1 and f2. Does anyone know how to design such a filter?

Before anyone asks it's needed for a research project regarding pulsed laser diodes. Most diodes have package inductance of around 5nH, which, when driven with series 50R, limits bandwidth to about 1GHz. I'd like to place this filter before final power amplifier (QPD1010) to generate an overshoot, that'll increase an effective bandwidth.

Hey all.

I am working on some personal project. I wish to design and test a folded cascode amp and use it for an LDO too.

I want to come up with some specifications for my OP Amp.

I want to set a certain gain, slew rate for output and power consumption. How can I decide what values should be a good target spec?

Say I set the gain target to be 60dB (which is modest for a folded cascode amp). Now how do I know whether it is attainable and I am not being limited by the technology itself. There is only so many tuning knobs that I could turn. At what point do I know I have squeezed the maximum performance out of that technology.

Also, how can I come up with reasonable specs for my project circuits (if I don’t have a customer setting the specs for me).

I understand that this is a very open ended question with no definite answer, but any advice from experienced designers would be appreciated!

I am using GPDK045 1v transistors. (If that helps)

​

Hello Everyone

I need a bit of help as I am assigned a semester project of 3 bit Programmable differentials Amplifier in 65 nm for -10 db to +10 db and bw is 350 MHz.

I'll highly appreciate the insights anyone can plz hit me up.

I need the guidance like what should be the architecture or some support material I should go through.

Thank u so much

Looking forward to your super guided thoughts

\#analog chip design

\#pga

\#cmos

\#tsmc

So my current SAR system is able to achieve better than 0.3m azimuth resolution using the SAR code written by HForsten, which is open source on github. Without this code, I am not able to reach 0.3m azimuth resolution. Thus without this code, my RADAR is completely uncontrolled.

Thus I do not understand what it means that I now fall under ITAR, I built this from commercial commodity parts that are all EAR99. Is the software controlled or the RADAR itself or both? How do I navigate this?

What is the difference between CST and HFSS for antenna design? What's the best ?