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u/Intelligent_Emu619

r/RISCV r/ComsatsLhr
▲ 27 r/RISCV

Rivet: a Rust RTOS with a RISC-V port, preemptive scheduling, and SMP support

I've been building Rivet, an RTOS in Rust, and have now open-sourced it.

The kernel has ports for ARM Cortex-M, RISC-V and Xtensa, with real preemptive scheduling and timer-driven context switching.

The RISC-V side currently includes the kernel scheduling/context-switch machinery and hardware/QEMU targets, while the broader project also includes dual-core SMP support on the ESP32-S3.

Other kernel features include:

  • Priority inheritance
  • Static task resources
  • No kernel allocator
  • Cooperative async tasks below the preemptive scheduler
  • Tickless operation
  • Synchronization primitives

I'm interested in feedback from people familiar with RISC-V trap/context-switch mechanisms and RTOS design, particularly around the architecture boundary between the portable kernel and the RISC-V port.

Repo:
https://github.com/habeelali/rivet-rtos

u/Intelligent_Emu619 — 7 days ago