r/RISCV

▲ 44 r/RISCV

AMD Radeon RX 6400 running on K3 Pico-ITX with openRuyi

A small graphics-related update from openRuyi.

AMD Radeon RX 6400 has been successfully brought up and is now running on a K3 Pico-ITX board with openRuyi.

Hardware / software:

- Board: K3 Pico-ITX

- GPU: AMD Radeon RX 6400

- OS: openRuyi

For anyone interested in the project, the openRuyi repo is here:
https://github.com/openRuyi-Project/openRuyi

u/JoannaNovaX — 22 hours ago
▲ 3 r/RISCV

SpacemiT K3: RTL8127 10GbE Controller, but only 1Gbps links?

EDIT:

Phoronix: "The 10 GbE SFP+, Gigabit Ethernet,". And maybe the SFP is fiber-only (not copper, which I try to use)?

/EDIT

"RTL8127 10GbE Controller", but I only get 1 Gbps links ... connected to

  1. 10GigE router port
  2. 2.5GigE router port
  3. 2.5GigE switch port (with very short cable)

My other systems do get 10Gbps resp 2.5Gbps links with the same router/switch/cable.

Do others have more success?

sander@spacemitk3:~$ lspci | grep -i net
0002:01:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8127 10GbE Controller (rev 08)
0004:01:00.0 Network controller: Realtek Semiconductor Co., Ltd. RTL8852BE PCIe 802.11ax Wireless Network Controller
sander@spacemitk3:~$

but

[Wed May 20 17:33:45 2026] dwmac-spacemit-ethqos cac80000.ethernet end0: Link is Up - 1Gbps/Full - flow control rx/tx
[Wed May 20 17:34:09 2026] dwmac-spacemit-ethqos cac80000.ethernet end0: Link is Down

[Wed May 20 17:34:15 2026] dwmac-spacemit-ethqos cac80000.ethernet end0: Link is Up - 1Gbps/Full - flow control rx/tx
[Wed May 20 17:36:00 2026] dwmac-spacemit-ethqos cac80000.ethernet end0: Link is Down


[Wed May 20 17:36:10 2026] dwmac-spacemit-ethqos cac80000.ethernet end0: Link is Up - 1Gbps/Full - flow control rx/tx
[Wed May 20 17:36:36 2026] dwmac-spacemit-ethqos cac80000.ethernet end0: Link is Down

[Wed May 20 17:36:42 2026] dwmac-spacemit-ethqos cac80000.ethernet end0: Link is Up - 1Gbps/Full - flow control off
reddit.com
u/superkoning — 1 day ago
▲ 39 r/RISCV

Happy RISC-V 16th Anniversary!

No one seems to mention here nor on X nor on RISC-V International official blog this year, but May 18 is the birthday of RISC-V. Yay!

reddit.com
u/omasanori — 2 days ago
▲ 72 r/RISCV

Another K3 arrived

Don’t live in a remote rural part of the most remote country on Earth if you want to be the first to receive things!

I haven’t received any tracking number so the arrival was a total surprise.

u/brucehoult — 2 days ago
▲ 36 r/RISCV+1 crossposts

GitHub - brucehoult/k3_ai: Utility to start a program on the A100 "AI" cores on SpacemiT K3 machines.

Now that people are starting to receive boards, I should make this available.

It lets you conveniently launch any Linux program, and all its children, on the A100 "AI" cores.

Examples:

# just run a single program on the A100 cores
ai as hello.s -o hello.o

# same thing but maybe 1ms faster
aix /usr/bin/as hello.s -o hello.o

# run a whole build. All processes started by `make` will run on the A100 cores.
ai make -j8 test

# start a shell on the A100 cores. All programs run from it will be run only on the A100 cores
ai bash

Tested on the preinstalled Bianbu. I have no idea yet whether the SpacemiT/Canonical cooperation will make this ability available on Ubuntu.

github.com
u/brucehoult — 1 day ago
▲ 6 r/RISCV

SpacemiT K3, Bianbu 4.0 and ... SFP ... not detected

I put a few different SFP 1GigE modules into the SpacemiT K3 SFP cage, but nothing happens: nothing in dmesg, nor "ip link".

It seems to be compiled in in the linux kernal.

Chatting with Google Gemini with all tests, this statement about device tree seems logical:

"If you get no output, the kernel was compiled with SFP support (CONFIG_SFP=y), but the current .dtb file booting your K3 Pico-ITX left out the physical layout definitions for the SFP cage. The hardware is essentially invisible to the OS."

Thoughts? Other experiences?

sander@spacemitk3:~$ zgrep CONFIG_SFP /proc/config.gz
CONFIG_SFP=y

sander@spacemitk3:~$ grep CONFIG_SFP /boot/config-$(uname -r)
CONFIG_SFP=y

sander@spacemitk3:~$ lsmod | grep sfp
sander@spacemitk3:~$ 

sander@spacemitk3:~$ sudo dmesg | grep -i sfp
sander@spacemitk3:~$ 

sander@spacemitk3:~$ ls /proc/device-tree/ | grep -i sfp
sander@spacemitk3:~$
reddit.com
u/superkoning — 1 day ago
▲ 3 r/RISCV

Alternative distro installs on Orange Pi RV2 ?

I have owned an Orange Pi RV2 for a year or two now, but I've barely used it.

Most of that is because I don't want to use Ubuntu on it. I'd like to try lighter weight distros.

However I only know how to boot up the official images from Orange Pi and Canonical, it's Ubuntu and I think a Debian Gnome thing (I forget). You flash them to a micro SD card and the system boots from it as is.

Many Linux distros offer RiscV images on their download pages.

However booting a distro on this is more complicated than a typical X86 PC desktop or laptop, and I don't know how to do it. With a typical PC I could just put the image on a USB stick and it would boot it.

I know this uses something called U-Boot? But I dont know... how to make that work with any arbitrary riscV distro image.

Any direction in getting other distros to boot on my system would be greatly appreciates.

side note: I tried imaging Chimera OS 's RiscV image to an SD card and it actually displayed something. But it was corrupted looking lines of blocks. That is the only time I've ever gotten something on screen from an alternative distro.

reddit.com
u/SleepyGuyy — 2 days ago
▲ 2 r/RISCV+1 crossposts

How to install any web browser on Ubuntu 24.04 RISC-V 64?

Hi,

I am running Ubuntu 24.04 RISC-V 64 on my DC Roma II as well as on QEMU (on ARM). Now I noticed that the Chromium version on the DC Roma II is severely outdated and the QEMU Ubuntu doesn't come with any browser at all. So I tried this:

lars@ubuntu-riscv64-QEMU-Virtual-Machine:~$ sudo apt update
[sudo] password for lars: 
Hit:1 http://ports.ubuntu.com/ubuntu-ports noble InRelease
Hit:2 http://ports.ubuntu.com/ubuntu-ports noble-updates InRelease
Hit:3 http://ports.ubuntu.com/ubuntu-ports noble-backports InRelease
Hit:4 http://ports.ubuntu.com/ubuntu-ports noble-security InRelease
Reading package lists... Done
Building dependency tree... Done
Reading state information... Done
All packages are up to date.
lars@ubuntu-riscv64-QEMU-Virtual-Machine:~$ sudo apt install firefox
Reading package lists... Done
Building dependency tree... Done
Reading state information... Done
Package firefox is not available, but is referred to by another package.
This may mean that the package is missing, has been obsoleted, or
is only available from another source
However the following packages replace it:
  gnome-browser-connector

E: Package 'firefox' has no installation candidate
lars@ubuntu-riscv64-QEMU-Virtual-Machine:~$ sudo apt install chromium-browser
Reading package lists... Done
Building dependency tree... Done
Reading state information... Done
Package chromium-browser is not available, but is referred to by another package.
This may mean that the package is missing, has been obsoleted, or
is only available from another source

E: Package 'chromium-browser' has no installation candidate
lars@ubuntu-riscv64-QEMU-Virtual-Machine:~$ 

So this didn't work. Is anyone here using Ubuntu 24.04 on RISC-V who has successfully installed any modern browser on it?

Thanks in advance!

reddit.com
u/I00I-SqAR — 2 days ago
▲ 7 r/RISCV

Booting Linux on a RISC-V core with no M, no A, and no CSRs at all. Pure RV32I

They said it could not be done.

Emulating this needs 100 lines of C++ code for the core, and 10 more for a trap unit.

How can we get preemtive multitasking, interrupts, M and U mode transition in a pure RV32I I am talking PURE. any opcode that is outside the 40 base ISA is invalid. Full Kernel.

Whats connected to it:
Full network stack (libslirp), package manager, desktop, stereo sound, keyboard and mouse, all running over memory mapped IO exclusively with thin linux driver wrappers to talk to software within linux.

If you want to check it out, or read the patches they are here in this branch: https://github.com/Gigantua/RiscVEmulator/tree/RiscV-LinuxOnBaseRV32I

I only want the mention the genuinely interesting parts.
Every instruction outside the Base RV32I ISA (40 instructions) is invalid.

Gap 1: no multiply/divide. That one is easy. Give the compiler the fallback in software for:
function call (__mulsi3, __divsi3, …) instead of emitting an opcode.

Gap 2: No atomics. Lots of patching. Normally they can be a NOP but we are not allowed to decode them, so they need to be patched away. See repo. This is a single core processor fundamentally.

Gap 3: There are no CSRs. A fixed RAM page (0x0F000000) holds what mtvec/mepc/mcause/mscratch/mstatus/mie should hold. Every csrr/csrw in the kernel's trap path is rewritten into an ordinary lw/sw against that page via a patch. There is no special logic about where we jumped to. There sits assembly code to read and store the registers.That means RV32I is executing microcode that is doing what the instruction would have done with a lw.

Gap 4: Interrupts without any CPU instruction. Single interrupt pin,
Timer/external interrupt hits a user process -> do_trap
Timer interrupt hits the kernel -> do_trap
ecall from userspace -> do_trap
Return to a user task -> trap_return

Gap 5: No packages for this arch. Package repo runs on the host and cross compiles any package that has source code for RV32i and hosts on port 8080. On the machine via rvcpkg add. Since we have a memory mapped eth0 with a working driver this just works. Works fine for zork, the sl locomotive and others.

Limitations: There is fundamentally no memory protection, but we get multitasking, and full linux access, wget etc just work. Without a mmu there is fundamentally also no dynamic library loading so framebuffer browsers could work, but none exist without dynamic loading.

Why is this exciting:

With core code as constexpr and really simple code, there is nothing stopping us fundamentally to run this in cuda (think of warp divergency, so thrust_group by next instruction at pc) or other experimental setups.

Busybox boots in about 1.5 seconds.

The system is elegant. Premtive interrupts, ecalls, M mode fall out of a trap system as a side effect, extremely reducing cpu complextiy.

"save state, enter M-mode, vector." Done in assembly at 0x0F000000. This is the "new" trick here I wanted to share. Lots of kernel patches later, we can have BASE RV32I and do the private register storing in assembly without a seperate instruction, to have full preemtive multitasking and a modern linux kernel with a network stack via a single lw instruction.

reddit.com
u/dangi12012 — 3 days ago
▲ 8 r/RISCV

Looking for RISC-V based SBCs with good mainline Linux support.

I'm looking for a Single-Board computer with a RISC-V CPU to test out the platform and develop some programs for it.

I'm not interested in fancy features such as the V extension, matrix multiplication, or anything that AI bros want. A simple RV64G CPU is fine for me, as long as it has enough power to spin up a desktop environment and maybe (maybe) a web browser.

What I am more concerned is having support for mainline Linux distributions, such as Debian or Fedora, for example. What I want is being able to go to the website of the distribution, download the RISC-V image, flash it into a SD card, and boot from it, totally avoiding (or as much as possible) the need to download from the manufacturer binary blobs or custom images of the OS.

reddit.com
u/MasterGeekMX — 3 days ago
▲ 17 r/RISCV

SpacemiT K3 Tips

Bruce Hoult pointed out that my SpacemiT K3 wasn't running at max frequency.

You can check with lscpu. If CPU Scaling is set lower than 100%, you can change the governor.

Available governors: cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_available_governors

Set governor for X100 cores: echo ondemand | sudo tee /sys/devices/system/cpu/cpufreq/policy0/scaling_governor

Set governor for A100 cores: echo ondemand | sudo tee /sys/devices/system/cpu/cpufreq/policy8/scaling_governor

You can read more here: https://www.spacemit.com/community/document/info?nodepath=software/SDK/buildroot/k3_buildroot/device/peripheral_driver/15-Cpufreq.md&lang=en

I have not tested the following things, but I asked SpacemiT about possibility to boot from USB or NVMe. Here are the links with more information. There is a UEFI test image.

https://www.spacemit.com/community/document/info?nodepath=hardware/eco/k3_pico/pico_user_guide.md&lang=en

https://spacemit.com/community/document/info?lang=en&nodepath=tools/user_guide/flasher_user_guide.md

reddit.com
u/LivingLinux — 3 days ago
▲ 61 r/RISCV

I received my SpacemiT K3 ... so logging requests are welcome again

Today I received my SpacemiT K3 (thank you, SpacemiT!) and ... sleek & smooth machine. Supercool.

NUC-size, nice connections (even an SFP+ interface), power-in via USB-C.

Setup of Bianbu 4.0 took 2 or 3 screens, and bingo ... working! Kernel is 6.18.3. GUI usage: very usable, medium speed, but a bit like a Celeron or N100.

If you want things tested / logged, create an issue with exact commands on https://github.com/sanderjo/SpacemiT-K3-X100-A100

u/superkoning — 3 days ago
▲ 32 r/RISCV

Older AMD GPUs that work on x86 are incompatible with RISC-V's Advanced Interrupt Architecture (AIA)

Looks like hardware that implements AIA like SpacemiT K3 are 100% incompatible with older AMD GPUs, at least the ones with the Caicos GPU and potentially others. This issue only seems solvable with a revision in the AIA standard, which would take years to take effect in new RISC-V hardware. RISC-V ecosystem contributors seem to suggest not using such ancient cards.

github.com
u/Icy-Concentrate2076 — 4 days ago
▲ 17 r/RISCV+3 crossposts

rvkit: A CLI/TUI toolchain for bare-metal Zig on RISC-V (CH32V003 & ESP32-C3)

Hi everyone,

Setting up a bare-metal Zig project on RISC-V microcontrollers typically requires manual memory configuration, writing board-specific linker scripts from scratch, and managing a fragmented toolchain (separate utilities for flashing and serial monitoring).

To solve this, I am developing rvkit, a CLI/TUI toolchain written in Rust that provides a unified workflow for Zig developers targeting RISC-V hardware.

Project link: https://github.com/karagure/rvkit

Core Features & Workflow

rvkit manages the entire development lifecycle through a minimal command interface:

  • rvkit new --board <target> <name>: Scaffolds a ready-to-build Zig project with preconfigured build.zig and auto-generated linker scripts.
  • rvkit build: Compiles the project using the native Zig toolchain.
  • rvkit flash: Flashes the compiled binary to the target MCU.
  • rvkit monitor: Opens a built-in TUI serial monitor.

Hardware Support

Board Architecture Flash Tool Under the Hood
CH32V003 RISC-V 32-bit wlink (WCH-LinkE)
ESP32-C3 RISC-V 32-bit esptool

Project Philosophy & Tech Stack

  • Toolchain: Written strictly in stable Rust (no nightly).
  • Target Language: Pure bare-metal Zig.
  • UX: Text-based. The serial monitor uses a terminal user interface (TUI) to keep dependencies low and integration tight.
  • Scope: Do one thing well (scaffold, build, flash, monitor). It does not attempt to replace your LSP (ZLS) or text editor.

Testing and Feedback Request

The toolchain is now functional, but it needs real-world testing. If you have a CH32V003 or an ESP32-C3 available, I would appreciate your feedback on the following:

  1. Toolchain Workflow: Does the binary installation and project scaffolding work out of the box on your platform?
  2. Hardware Edge Cases: Does the flashing tool or the TUI serial monitor fail under specific configurations?
  3. Code Review: For Rust and Zig developers, any feedback on the implementation or architecture is welcome.

Please open an issue on GitHub or leave your technical feedback in the comments below.

Thanks.

u/PetiteBisc0tte — 3 days ago
▲ 43 r/RISCV+1 crossposts

We partnered with BayLibre to bring Android 16 to RISC-V — fully open source, running on SpacemiT K1

We're excited to share that SpacemiT has partnered with BayLibre to successfully run Android 16 on the SpacemiT K1 SoC (RISC-V RVA22 + RVV 1.0).

What was achieved:

  • Android kernel 6.19 running with K1 vendor kernel 6.6 drivers
  • Vulkan support enabled via Imagination GPU in mesa3d
  • Generic HAL Utilization: We leveraged Baylibre’s Android generic Hardware Abstraction Layer (HAL) for essential functions, including thermal management, USB, and audio.
  • Full Android 16 device config built for SpacemiT RISC-V. Boot time under 2 minutes on BananaPi F3 (K1 platform)

The entire project was built on 100% open-source software — AOSP, mainline kernel, no NDAs, no proprietary blobs. Anyone in the community can rebuild the image from scratch.

Source code: https://github.com/BayLibre/android_manifest
Full write-up: https://baylibre.com/blog/baylibre-partners-with-spacemit-to-bring-android-16-to-risc-v/

We welcome the community to test, contribute, and help push RISC-V + Android forward.

Questions welcome!

u/Icy-Primary2171 — 4 days ago