The madman strikes again.

Monthly update from openRuyi, a Linux distribution for RISC-V.

2026.06 is mostly routine platform work: desktop, kernel/toolchain, virtualization, and security fixes.

Details:

https://openruyi.cn/news/2026-06/release

I will be posting daily here: https://r-tty.blogspot.com

From the first attempts to run bios_emulator, to the complete native RISC-V 64-bit VideoBIOS.

And apparently there's also a set of patches for the A100 waiting in the queue.

"A pair of custom RISC-V processors drive the ASICs.", with those ASICs enabling reusing old memory banks.

https://www.theregister.com/systems/2026/06/29/zuck-saves-meta-bucks-by-reusing-memory-from-old-servers-with-a-custom-cxl-asic/5263483

Hey everyone, I'm a CS student focused on low-level systems. I just finished writing a working RV64I interpreter and I want to expand it to learn more.

I’m currently torn between three directions:

1. Simulated Hardware Accelerator: Adding a memory-mapped device to experiment with hardware acceleration (e.g., HPC/math operations).
2. Full OS Support: Adding M/A extensions, CSRs, PLIC/CLINT, and Sv39 virtual memory so it can boot xv6.
3. JIT Compilation: Upgrading the execution loop from a basic interpreter to a JIT compiler for performance.

Which of these paths taught you the most? If you have other project ideas that build off a RISC-V core, I'd love to hear them!

With the leak of Qualcomm acquisition negotiations, I'm curious as to Tenstorrent's market prospects. While they have been doing innovative work on the licensing front, I haven't heard much about their hardware sales.

Why did their AI hardware not take off? What are the prospects for Ascalon and future CPUs? How much of this is due to the fab oversubscription and high interest rates?

I was really hoping Tenstorrent would emerge as a competitor to the existing oligopolies, even if they are propped up just to ensure a second source supplier. A purchase by IBM or a roll-up with a smaller player would be much healthier for the market.

But it sounds like volume is a limiting factor that enables the big players to shut out competitors?

Edit: I'm not asking why I don't have a leading edge CPU. I'm asking why TensTorrent would be in serious negotiations instead of financing another round.

I bought a 10G RJ45 SFP Copper Module 10G/5G/2.5G RJ45 Port Transceiver on Ali (24 euro all-in), plugged it in in my Spacemit K3, and ... bingo. Just working: linespeed on my 8Gbps Internet connection.

sander@spacemitk3:~$ iperf3 --bind-dev enP2p1s0  -P50 -R  -c ams.speedtest.clouvider.net -p 5208 | grep SUM
[SUM]   0.00-1.00   sec   929 MBytes  7.79 Gbits/sec                  
[SUM]   1.00-2.00   sec   916 MBytes  7.69 Gbits/sec                  
[SUM]   2.00-3.00   sec   923 MBytes  7.74 Gbits/sec                  
[SUM]   3.00-4.00   sec   932 MBytes  7.82 Gbits/sec                  
[SUM]   4.00-5.00   sec   914 MBytes  7.67 Gbits/sec                  
[SUM]   5.00-6.00   sec   934 MBytes  7.84 Gbits/sec                  
[SUM]   6.00-7.00   sec   944 MBytes  7.92 Gbits/sec                  
[SUM]   7.00-8.00   sec   936 MBytes  7.85 Gbits/sec                  
[SUM]   8.00-9.00   sec   946 MBytes  7.93 Gbits/sec                  
[SUM]   9.00-10.00  sec   944 MBytes  7.92 Gbits/sec                  
[SUM]   0.00-10.00  sec  9.19 GBytes  7.89 Gbits/sec  8483             sender
[SUM]   0.00-10.00  sec  9.10 GBytes  7.82 Gbits/sec                  receiver
sander@spacemitk3:~$

... boring can be good.

So very cool

If you ordered in the first day or so after 00:00 UTC+8 May 11 (9 AM May 10 in PDT, noon EDT, 5 PM UK, 6 PM western EU, 2 AM May 11 eastern Aus) please comment with the exact date/time in your local time zone (and say which one!) or UTC and your order status, when you received shipping confirmation and/or it arrived (if it has), and which reseller you used.

I mean people who bought a board, not those seeded with review ones.

Over on r/spacemit_riscv someone said they ordered from Arace on May 11 and just now got a shipping notification.

Sipeed was showing photos of K3 in stock on May 11 ...

https://x.com/SipeedIO/status/2053753308003889456

... and orders ready to ship on May 16 ...

https://x.com/SipeedIO/status/2055549071931404291

Someone must have received those!

Sipeed also posted that they received 100+ orders in the first 10 hours. They might not have had that much stock.

Have other resellers had similar posts that I missed?

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Hi
Have you come across any books about RVV-1.0 intrinsic programming?
I know my way around AVX but RVV still feels uncomfortable...
Any advice?

Hi,

I am currently unable to find a place were the privileged spec is described from a behavioral standpoint. For example, for when an exception or interrupt occurs, I guess a possibility is to go and get that info from the CSR descriptions. However, iss there some place were it can be seen as a 'recipe'?

Something like:

When an exception occurs, `mcause` gets written with the corresponding exception code, then pc is set to `mtvec`, etc.

I have read that all interrupts and exception will be handled in M-Mode per default. Except the specific bits in the CSR's mideleg and medeleg are explicitly set. Because I want port my own small kernel to RISC-V and I want use OpenSBI too, what is the hand-off state from OpenSBI according interrupts and exception? Are some of them forwarded to S-Mode? Because I think I can't modify the M-Mode registers mideleg and medeleg in S-Mode.

Thanks in advance!