r/RISCV

Hola, me gustaría compartir este excelente conjunto de herramientas/framework de bajo nivel. Es un framework basado en Python, específicamente un generador de ISA de redirección (RIF). Aunque ya cuenta con plugins y ejemplos para ROMs de Game Boy Advance, creo que con el desarrollo y la colaboración adecuados, puede convertirse en algo mucho más útil, versátil e incluso "ELEMENTAL". Visita el sitio web o el repositorio para echar un vistazo, descargar una versión y ejecutar pruebas, o quién sabe, tal vez incluso iniciar un proyecto con lo que ya está hecho, o simplemente colaborar en el proyecto. ¡Ah! Por cierto, debo aclarar que este no es mi proyecto; solo lo estoy presentando y, por supuesto, lo comparto porque creo que tiene mucho potencial.

Hey guys,

I’m a final year student aiming for RTL design roles. I was thinking of building a 32-bit RISC-V (RV32I) core from scratch as my final year project.

But is a basic RV32I core still relevant in 2026, or is it too common now?

Should I instead add something interesting like pipeline, cache, branch prediction, custom instructions, formal verification, etc. Or maybe do something completely new with RISC-V?

If you were in my place, what kind of project would you build to actually stand out for an entry-level RTL role?

Any suggestions from people working in RTL/ASIC/FPGA would be really helpful :)

Wonder where one can get ones hands on these...?

As part of a current LF Mentorship, we’re fortunate to have mentees Aryan and Rohit working with RVI to make the Extension Landscape more complete and useful.

Many previously missing extensions have been added, the backend organization has been improved, integrated data from UDB (which we now consume directly and automatically), and introduced the ability to create custom profiles and drill down into individual extensions.

There is a good amount of work to complete, but we believe it is time for an RFC in order to set a roadmap that meets the ecosystem needs. 

Please, give it a try [1] and share your feedback either via this thread or opening an issue here [2].

1 - https://rpsene.github.io/riscv-extensions-landscape/

2 - https://github.com/rpsene/riscv-extensions-landscape/issues 

I am embedded systems engineering student, interested in compilers, system programming with c/c++ and rust, and good enough with asm. Is there any recommendations for an open source running project i can contribute to without being an expert.

I read the article Grinberg did and I come at this argument from a somewhat different place, I’m an embedded engineer from Trinidad and Tobago, what people would traditionally call the Third World… Here, the difference between a ten cent RISC-V microcontroller and a several dollar alternative is not academic and neither is having an architecture that a small company, student, or individual engineer can understand, modify, and build around without asking permission… So when I read what Grinberg wrote some of its criticisms made sense to me, but some of his assumptions did not… so I thought I’d do a response, it might not reach far but I love RISC-V enough to at least defend it from where I stand.

And will it reach a state comparable to intel/amd world soon?

Been meaning to lose less time and energy with distractions, and this weekend, while messing around with it, I realised my Sifive Premier P550 can now do all I need for most of my work.

I can now use Chromium 151, which has impressive performance gains over Firefox. I have 2 profiles (one for work, one for my personal stuff).

Most of my work is web-based, so this works out just fine.

I haven't opened any social media here (other than this to share my experience). I am listening to music, but even YouTube 480p works just fine.

There is so much less *noise*. I started doing some things I have been putting off for ages, like building a project management schedule.

The fact that it is a bit slower makes me think "do I really need to do that right now?".

Any questions are more than welcome.

I am running Debian 13 Trixie with a 6.6 vendor kernel.

To continue grow riscv beyond mcu's we need some standardized way render desktop / phone shell.

Here is couple ideas i here.

• Good enough to run desktop environment / kiosk applications
• Like older Mali in arm ecosystem
• Unified memory
• Same MMU (Sv39/Sv48) as main cores
• Tiller architecture
• No display controller (only rendering in buffer in memory)

What do you think?

IT seems to me that good part of underlying fundamental assumptions for RISC-V just got rejigged if not outright smashed by latest AI advances.

They seem to be on verge of being capable of reimplementing whole compiler/assembler/debugger backends to fit the ISA.

If so, how many of RISC-V fundamentals are still needed ? Maybe the time is coming for RISC-VI or something like that to be optimized for new reality ?

>WCH CH32V407 and CH32V467 are new 200 MHz RISC-V microcontrollers with a built-in 10/100 Mbps Ethernet MAC + PHY, a USB 2.0 high-speed (480 Mbps) host PHY, up to 8 MB on-chip PSRAM, and a range of peripherals for industrial IoT & edge AI applications.

>Both are based on the company’s Qingke V3V core with RVV vector extensions, delivering 4.11 CoreMark/MHz, a score higher than a typical Arm Cortex-M4 core. The main difference between the CH32V407 and CH32V467 is that the latter comes with 4 MB or 8 MB PSRAM, making it more suitable for display/HMI applications.

"This is a new variant of Ascalon X and Tenstorrent engineers are working on getting the RISC-V CPU core support ready for upstreaming into the open-source GCC compiler. RISC-V's zvkng is a set of vector cryptographic extensions.

With dropping the crypto and reducing the throughput, it sounds like the Ascalon XG could end up being an export model for Tenstorrent to China or similar markets. And the patch does note, "the global version of Ascalon X" so would align if that global is in terms of non-US/worldwide."

Hi everyone,

I'm currently planning to apply for next year's LFX Mentorship, particularly Term 2, and I'm interested in working on a RISC-V-related project.

I'm an undergraduate ECE student and have some experience with systems-related projects and tools such as QEMU and HEMI. However, I know that the RISC-V ecosystem goes much deeper, covering areas like architecture, emulation, compilers, operating systems, firmware, verification, and more.

I have roughly a year to prepare, and I don't want to spend that entire time randomly jumping between different RISC-V topics without building useful depth.

I'd really appreciate some guidance from people who have worked on RISC-V projects or participated in LFX mentorships:

• What level of knowledge do mentors/selection teams generally expect from applicants?
• What topics should I focus on during the next year?
• Should I first build a strong understanding of computer architecture, or focus more on practical contributions to projects?
• Are there any RISC-V open-source projects that are particularly beginner-friendly but can eventually lead to meaningful contributions?
• What would be a realistic preparation roadmap for someone aiming to apply next year?

My goal is not just to learn RISC-V superficially for the mentorship application. I want to develop enough depth that I can actually contribute to a real project and become comfortable working with difficult systems topics.

Any advice, resources, or suggestions based on your experience would be really helpful.