▲ 39 r/RISCV
Happy RISC-V 16th Anniversary!
No one seems to mention here nor on X nor on RISC-V International official blog this year, but May 18 is the birthday of RISC-V. Yay!
u/omasanori — 2 days ago
u/omasanori
▲ 4 r/RISCV
Call for RISC-V International Board of Directors Candidates (Nomination Deadline: June 6)
riscv.orgu/omasanori — 5 days ago
▲ 26 r/RISCV
RVV Benchmark Results Updated for Tenstorrent Ascalon X and Ascalon S
u/camel-cdr-'s RVV benchmark published the up-to-date results of Ascalon X and Ascalon S from the TT-Ascalon family by Tenstorrent. The lesser-known Ascalon S is a high-efficiency core while Ascalon X is a high-performance core, both compliant to RVA23. The results are measured on an FPGA-based simulation platform, not on a manufactured silicon chip.
u/omasanori — 6 days ago
▲ 11 r/RISCV
How Secure is a High-Performance RISC-V Core? A Spectre V1 Case Study on XiangShan Open-Source CPU
dl.acm.orgu/omasanori — 9 days ago
▲ 3 r/RISCV
[2605.08229] REPTILES: Repeated Tiles of Sargantana, a RISC-V multicore based on OpenPiton
arxiv.orgu/omasanori — 10 days ago
▲ 12 r/RISCV
[2605.10860] Closer in the Gap: Towards Portable Performance on RISC-V Vector Processors
arxiv.orgu/omasanori — 10 days ago
▲ 31 r/RISCV
The Development of SpacemiT X200 Based on XiangShan Kunminghu V2 Completed
From the draft of upcoming XiangShan biweekly report:
> The development of X200, SpacemiT's third-generation high-performance RISC-V processor core derived from XiangShan Kunming Lake V2, has been completed. Based on a conventional cloud-computing processor core, X200 has been specifically optimized for cloud-side Agent applications and flagship end-device Agent applications. Its SPECint 2006 performance reaches 16.0 points/GHz, and its single-core frequency can reach 3.3GHz. Compared with X100, its performance per core has improved by more than 100%, reaching 50 SPECint 2006 points/Core.
According to the paragraph above, the performance of SpacemiT's next processor core will reach somewhere between SiFive P670 and P870.
u/omasanori — 10 days ago
▲ 13 r/RISCV
[somewhat off-topic] The SPEC CPU 2026 Benchmark Released
The SPEC CPU: The Next Generation conference paper explains the background, motivation and design of the benchmark.
u/omasanori — 11 days ago
▲ 7 r/RISCV
Ziccid Extension for Instruction and Data Coherence and Consistency To Be Ratified in June
riscv.atlassian.netu/omasanori — 14 days ago
▲ 5 r/RISCV
u/omasanori — 24 days ago
▲ 3 r/RISCV
This is an alternative approach for forward-edge CFI that is covered by the Zicfilp extension.
u/omasanori — 24 days ago
▲ 7 r/RISCV
u/omasanori — 25 days ago
▲ 40 r/RISCV
u/omasanori — 26 days ago
▲ 33 r/RISCV
u/omasanori — 28 days ago