u/TJSnider1984

Wonder where one can get ones hands on these...?

"This is a new variant of Ascalon X and Tenstorrent engineers are working on getting the RISC-V CPU core support ready for upstreaming into the open-source GCC compiler. RISC-V's zvkng is a set of vector cryptographic extensions.

With dropping the crypto and reducing the throughput, it sounds like the Ascalon XG could end up being an export model for Tenstorrent to China or similar markets. And the patch does note, "the global version of Ascalon X" so would align if that global is in terms of non-US/worldwide."

Much as I'm a fan of AMD's processors, and firmly believe that Venice rocks, a reality is that the Vera is a strong processor, and we shouldn't discount it completely merely because it's NVidias. However given the lack of hardware available for truly independent reviewers to test at their leisure, it's going to be a while till the actual data are available.

George's article is a medium technical article, and can be summarised by "After 45 pages, my position on Vera is more positive than my position on the Vera whitepaper."

It does sound like they may have issues with per-core multi-threading, but time will tell. So I'm marking this as a "rumour"...

Anyone know what that "real silicon" P870-D product is?

As per github repo:

"768-Core Native RISC-V AI Compute Cluster

The Cluster Server RV2768 is a RISC-V-based cluster server in a 2U, 19-inch rack form factor, integrating up to 48 SpacemiT K3 processors and compliant with the RVA23 profile defined by RISC-V International.

RVA23 targets general-purpose application processors, requiring support for Vector and Hypervisor extensions, and represents a modern performance standard for AI and high-performance workloads. The system delivers 768 native RISC-V cores, making it well-suited for large-scale application builds and full operating system compilation.

With a multi-node cluster architecture and full hardware virtualization, the server streamlines CI/CD workflows and accelerates the RISC-V software ecosystem. Leveraging vector extensions, it delivers up to 2880 TOPS of AI compute and supports up to 1536 GB of memory for concurrent AI inference workloads.

• 2U chassis supporting up to 48 compute nodes (384 CPU cores + 384 AI cores)

"

Sounds like we're finally going to get a decent build/cluster machine..

Looks like a picture of this might be up on https://www.reddit.com/r/spacemit_riscv/comments/1v7u0k2/view_of_k3_shelf_array_server_k3_picoitx_and_k3/

I did a fresh install of Debian Trixie in text mode... and it should be showing a text console and login, but I only get the first line "/dev/sda1 ... " and then only the blinking cursor.

I can ssh into it fine and play with stuff, but even though I've forced the text console 5 ways from sunday, ie. all the systemctl, it still never shows up past that first line..

Any suggestions? I've tried playing around with various configuration settings... to no avail..

This is on a DS1621+ (AMD) with DSM 7.3.2-86009 Update 4

"AMD first introduced the Ryzen AI Embedded X100 family when it launched the Ryzen AI Embedded P100 family in January 2026, delivering up to 50 TOPS of AI performance. However, at the time there were very few details about the X100 family, just that it would offer higher CPU core counts and AI TOPS performance, and this latest announcement fixes that.

AMD claims the new X100 series processors are expected to deliver up to 2.1x higher multithread CPU performance (CoreMark), an 1.7x graphics performance uplift (OpenGL, GFXBench 5.0.0), and 3.5x higher token generation throughput with 1.4x faster time-to-first-token (TTFT on llama-bench) for accelerating physical AI workloads compared to equivalent Intel Core Ultra Series 3 processors. "

I was wondering what happened to the X100 family..

"Normalizing the NVIDIA Vera Whitepaper Numbers to AMD EPYC Turin

Since NVIDIA dropped its Vera whitepaper just before AMD’s Advancing AI 2026, where we expect to learn more about AMD’s next-generation “Venice” CPU. Companies typically do this because the valid comparison is versus the outgoing generation rather than the concurrent generation. Since we are still under embargo for AMD’s Venice, I wanted to provide a framework to help our readers create a useful comparison framework for NVIDIA’s Vera results. The key points I want to cover are:

• Socket and per-core memory bandwidth gains
• Core-to-Core Latency, Chiplet Construction, and Glue
• Important Cores and SMT Threads
• Then we will have a big discussion on normalizing the SPEC CPU2026 performance, and a framework for evaluating AMD EPYC Turin versus NVIDIA Vera through a fairer lens.

These are all framing techniques we have seen in the industry before, so this may not be ground-breaking for many STH readers. At the same time, we want to help folks get more context about what was presented, why, and how to get to an alternate comparison point."

"As a follow-up to the article over ROCm 7.14 being tagged, AMD has formally announced the availability of ROCm 7.14 and it's their new production release rather than being a tech preview.

Since ROCm 7.9, the 7.9+ releases have served as "tech preview" releases while ROCm 7.0/7.1/7.2 were stable series. Up to now my assumption was that the ROCm 7.9+ tech preview releases would culminate with ROCm 8.0 being stable. Now as quite a surprise, ROCm 7.14 was announced today -- ahead of next week's AMD Advancing AI event -- as the new production release. Quite the version numbering mess.

ROCm 7.14 "marks the start of our future production releases. users on 7.2 and older are encouraged to migrate and follow the transition guide on rocm docs" per the AMD documentation. Beyond the build system overhaul with TheRock, new to ROCm 7.14 is officially adding support for the Ryzen AI 400 series, including the new Ryzen AI Max+ PRO 495 / PRO 490 / PRO 485 products and lower-end Ryzen AI 430/440 series offerings.

ROCm 7.14 also adds official support for RHEL 9.8 and RHEL 10.2, SUSE Linux Enterprise 15 SP7 / SLES 16 / Debian 13 for the Instinct MI350P hardware, and more."

So how much buffer does TSMC have, and how long before this slows production? For Semi's this is one of the big risks of the Hormuz war..

STH goes into their usual decent depth on the tradeoffs.

And apparently there's also a set of patches for the A100 waiting in the queue.

[ Removed by Reddit on account of violating the content policy. ]

Just a reminder that AMD is still moving ahead with FPGA SoCs...

So, yes it's MLID... so apply appropriate amounts of salt.. ;) However this does jive well with the recent news about AMD hitting production scale up.. which is public knowledge. MLID suggests it is B0 silicon, so they've fixed a few bugs in their first release and gone through that test verification cycle. The interesting part of the leak is that they apparently already ready for X3D... can't tell if that extra B0 cycle gave them time to add that in or if it was always in the cards, but that sure would broaden the product range at launch, and potentially lead to a more interesting Computex next week. Time will tell.