How reliable is VHDL to Verilog conversion?
Long story short, I'm beginning the long journey of learning FPGA development with the long term goal of making an FPGA version of my MCU based embedded 2d GPU.
I am leaning towards VHDL mostly because as a software engineer I not only like strong typing, but I hear that VHDL has the advantage over verilog of being conceptually different than iterative programming languages to not fall into bad normal software programming habits. The verbosity is not (at the current moment) a turn off (that could change :) ).
However, a lot of tools seem to be focused on Verilog instead of VHDL. While I have an Arty-S7 7000 board, I am starting off learning using the Nandland Go Ice40 board using open source toolchains (so Yosys). It seems that Yosys doesn't support VHDL except via plugins that half the search results claim stop working after some upgrades.
I already have a Verilator C++ application up and running that successfully pipes a Verilog based VGA signal into an SDL2 window for fast iteration testing. However, afaict Verilog doesn't have VHDL support.
Yosys is also used for some asic designs, for example if I wanted to experiment with tiny tapeout.
It seems like there's some support for the tool GHDL to convert from VHDL to verilog, and I can easily build a pipeline to do that conversion automatically.
Is the VHDL -> Verilog transpilation process reliable enough to use, or am I setting myself for a debugging headache due to complications from that conversion? Should I just focus on V/SV instead and save the headache?