RTL design - Guidance
I am working in a networking hardware startup in Bengaluru. I completed around 1 year here. Company itself is a Gen 1 startup and only around 18 months old, so many flows were not properly available when I joined.
In this one year I worked on many things around RTL/design, but I feel I did very less actual RTL design. Some work I did:
Replicating setup from existing blocks to our block.
Creating setup for top-level RAL flow for software and DV.Writing some CSR related RTL/work.
Creating Makefile based flows.Writing some Python scripts to assist DFT work.Running lint, fixing minor lint issues and adding waivers.Integrating some Synopsys IPs, reading their documentation and doing setup.Creating Joules setup, running clock gating reports and trying to improve low clock-gating areas.Running synthesis through Makefiles and trying to understand synthesis reports.
I can read timing reports to some level, but I did not get chance to do actual timing closure/fixes.
Some waveform debug and minor RTL fixes.
Running Formality. I debugged a few minor failing points, but not much deep experience.
For most of these tasks, I also took help from Cursor AI. I am worried because many setup/automation type tasks can become easier with AI, and for Gen 2 project most basic flows will already be present.
Now we are near RTL freeze and I am not getting much work. I feel like I did everything around design except actual design. I have not really written a proper RTL module from scratch based on a spec.
What I really want is to improve microarchitecture skill. Suppose someone gives a spec, I want to know how to think:What registers are needed?Where FIFO is needed?How to handle backpressure, latency, throughput, reset, errors, arbitration etc.I want to build intuition like a real RTL designer, not just run flows or fix small issues.
I thought of writing my own IP and comparing with existing Synopsys IP, but if I start with something big like DMA controller, maybe I will spend forever and still not understand if my architecture is wrong. I am confused what projects to start with and what learning path to follow.
Since next project may take around 2 more months, I want to use this time seriously. My goal is that in next project I can demand ownership of a small block and take responsibility from microarchitecture to signoff.
I also have few career questions:
What kind of work does a junior RTL/design engineer with 1-2 years experience get in companies like Nvidia, Qualcomm, Samsung, Google, Microsoft, Analog Devices, etc?
If I want to switch to such companies, what should I prepare for interviews?
What kind of RTL/microarchitecture/design questions are usually asked for someone with around 1 year experience?
What projects can I do in next 2 months which will actually help me become better?
Any good resources for industry-level RTL and microarchitecture? Most online material feels either college-level or too random.
For India/Bengaluru, what can be expected salary range for 1-year RTL engineer in good product/MNC companies?
I am from a tier 1 college but unfortunately I don’t have seniors/friends whom I can discuss these things with.Any honest advice, roadmap, resources, project ideas, or interview experiences will really help. Thanks.
#vlsi #rtldesign