Hey everyone, I'm a CS student focused on low-level systems. I just finished writing a working RV64I interpreter and I want to expand it to learn more.

I’m currently torn between three directions:

1. Simulated Hardware Accelerator: Adding a memory-mapped device to experiment with hardware acceleration (e.g., HPC/math operations).
2. Full OS Support: Adding M/A extensions, CSRs, PLIC/CLINT, and Sv39 virtual memory so it can boot xv6.
3. JIT Compilation: Upgrading the execution loop from a basic interpreter to a JIT compiler for performance.

Which of these paths taught you the most? If you have other project ideas that build off a RISC-V core, I'd love to hear them!

Hey everyone, I'm a CS student focused on low-level systems. I just finished writing a working RV64I interpreter and I want to expand it to learn more.

I’m currently torn between three directions:

1. Simulated Hardware Accelerator: Adding a memory-mapped device to experiment with hardware acceleration (e.g., HPC/math operations).
2. Full OS Support: Adding M/A extensions, CSRs, PLIC/CLINT, and Sv39 virtual memory so it can boot xv6.
3. JIT Compilation: Upgrading the execution loop from a basic interpreter to a JIT compiler for performance.

Which of these paths taught you the most? If you have other project ideas that build off a RISC-V core, I'd love to hear them!