u/Past_Tangerine_847

Built a quantum software optimization layer and validated it on real IBM Quantum hardware (up to 152 qubits)

Built a quantum software optimization layer and validated it on real IBM Quantum hardware (up to 152 qubits)

Hi everyone,

Over the past several months, I've been building Quantum Knife OS, a proprietary software layer designed to improve execution quality on today's noisy quantum hardware.

This week I completed another round of validation on real IBM Quantum hardware (IBM Fez, IBM Kingston, and IBM Marrakesh).

Some results from the latest validation:

  • Executed successfully on real IBM Quantum hardware
  • Tested on benchmark scales up to 152 qubits
  • Up to 8.14× higher measured correlation than the baseline implementation on the 98-qubit benchmark
  • Approximately 12× higher measured correlation at 16 qubits
  • Strong retained correlation across the evaluated benchmark suite
  • Achieved entirely through software, without modifying the underlying quantum hardware

The motivation behind this project is simple.

Today's quantum computers are limited by hardware noise, topology constraints, and execution quality. Rather than designing new hardware, I'm exploring how much improvement can be achieved through a software optimization layer.

To protect my intellectual property, I'm not publishing the proprietary mathematics, optimization algorithms, or implementation details at this stage. However, I am sharing:

  • IBM Quantum hardware validation reports
  • IBM execution screenshots
  • Raw IBM job data
  • Benchmark comparisons
  • Performance summaries

I'm interested in technical feedback on the validation methodology, benchmarking approach, and presentation of the results.

If anyone here works in quantum computing, quantum software, or quantum compiler optimization, I'd genuinely appreciate your thoughts and discussion.

This is the first public milestone of the project, and there's still a lot more work ahead.

Thanks for reading.

https://preview.redd.it/pyga6wn7h8bh1.png?width=1915&format=png&auto=webp&s=bfc5f0e77c6e0e264355da1abec1b7d129438bd4

https://preview.redd.it/ghvz3wn7h8bh1.png?width=1918&format=png&auto=webp&s=65597f34aaa1370893eb7569f91e64d8e32dcc86

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u/Past_Tangerine_847 — 1 day ago

Building a 10,000-node RF Metamaterial Chip (5 GHz) as an Independent Researcher — Seeking Lab Access & Collaborators (India)

Hey r/Semiconductors,

I'm an independent researcher from Hyderabad, India working on Project Topo-RF - a passive RF metamaterial structure targeting 5 GHz (S-Band/C-Band).

What it is:
A 10,000-node capacitively-coupled gold resonator mesh on a high-resistivity quartz substrate. 100×100 grid, 150µm pitch, 5-10µm inter-node gaps. The goal is to characterize group delay and dispersion behavior of this topological mesh vs. classical sequential transmission lines.

Current status:

  • GDSII layout file ready (project_topo_rf_phase0_2port.gds)
  • Full fabrication SOP ready (LOR+S1813 lift-off, Ti 5nm + Au 200nm, e-beam evaporation, Class 1000 cleanroom)
  • Looking for cleanroom access in India (exploring IIIT-H FabLab and IIT Hyderabad)

Asking for:

  1. Anyone with experience accessing university fabs in India as an external/independent researcher - what was your process?
  2. RF engineers or researchers interested in collaborating on this project
  3. Any technical feedback on the approach

Happy to share the engineering docs with anyone interested. DM open.

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u/Past_Tangerine_847 — 4 days ago