For fab/equipment engineers: When a 15–20 year old Ebara/TEL/SCREEN/etc. tool goes down and your internal team can’t figure it out, who do you actually call?
OEM? Former employee? Contractor? Someone else?
And have you ever actually paid an independent engineer to solve something like this??
Should I stay at a job I like for the experience, or leave because I hate the location?
I’ve been working in the semiconductor industry in Idaho for about five years since graduating college. This is my first job, so I don’t have any experience outside of this industry.
The difficult part is that I actually really like my job. I recently got promoted, I have a great manager and coworkers, and I genuinely enjoy the work I do. I also think getting experience with a new fab startup would be really valuable for my résumé and career.
The problem is… I really hate living in Idaho.
I’m not an outdoorsy person at all, and I grew up in a big city. I miss having more things to do, shopping, professional sports, and just having a larger-city environment. I also find the state very conservative, and I’m increasingly uncomfortable with the idea of raising a family here in the future.
So I feel stuck. My work situation is great, but my personal life and location are not.
I’ve been hoping to get startup experience with a new fab, but the schedule keeps getting pushed back. I don’t know how long I’ll actually have to wait, and I’m starting to question whether it’s worth staying just for that experience.
What would you do in my situation?
Would you stay another 1–2 years to get the fab startup experience and then use it to move to another company/location, or would you start looking for a new job now and prioritize getting out of Idaho?
I’m especially interested in hearing from people in semiconductors who have changed companies/locations early in their careers.
I had to leave my CSE role with KLA 3 years ago for personal reasons. I received a call a few months ago that they might have a position for me available at a different location. As of yesterday, it's official. I'm back the industry I love!
I’ve been working with a circuit that can generate both PTAT and CTAT voltages with adjustable slopes through switching.
I’m curious about the possible applications of having variable slope PTAT and CTAT outputs. Apart from conventional temperature sensing, could this kind of circuit be useful in other circuit applications?
I’d really appreciate any ideas or suggestions.
I want to make sure my understanding of our project milestone flow aligns with broader industry standards. I’d love some feedback or corrections from those with more tape-out experience.
Here is how I understand the flow:
P0.3 (Early RTL): Basic Lint runs continuously/nightly to catch obvious typos and syntax issues as code is being written.
P0.5 (RTL Design Correction / Freeze): This is the major, formal Lint sign-off. Code is feature-complete. This is when we deep-dive, group errors by tag, fix actual RTL bugs, and negotiate targeted waivers with IP designers.
P0.8 (Verification & Pre-Synthesis Sign-off): CDC checks are finalized and signed off. The RTL is officially locked.
P1.0 (Synthesis Complete): The clean, signed-off P0.8 RTL is handed over to run Logical Synthesis (e.g., Design Compiler) to generate the gate-level netlist.
My questions:
Does this P0.3 ➡️ P0.5 ➡️ P0.8 ➡️ P1.0 progression for Lint/CDC/Synthesis match what you see in standard ASIC flows?
At what exact point do you usually start running CDC? Is it strictly after P0.5 Lint is clean, or does it run in parallel?
Thanks in advance
Light particles intended for quantum communication can lose their usefulness because of the order in which they emerge. A semiconductor experiment has shown how controlling that sequence can produce photons that interfere much more reliably.
The work brings quantum dots closer to supplying high-quality light for advanced quantum communication schemes. It also exposes a practical tradeoff: improving photon coherence does not automatically make both particles easy to collect.
Scientists from the University of Basel, Paderborn University and Ruhr University Bochum reported the findings in Physical Review Letters. Their device uses an optical cavity to change how quickly a tiny semiconductor structure releases its two photons.
I'm currently looking for a topic for my senior/final-year project.
I'm particularly interested in the intersection of: FPGA / RTL design
wanna learn about Neural Network accelerators and Digital IC / VLSI design
I've been working on vhdl language for a while.FPGA-based digital design, and some embedded systems. I'm also interested in learning more about Verilog/SystemVerilog, ASIC design and AI hardware.
If you were an undergraduate student with access to an FPGA board and basic electronics lab equipment, what kind of project would you choose today in this area?