Would love recos of books and manuals.

WHat are you guys reading these days to build domain expertise?

Hi, I just graduated B Tech ECE and got a job at a semiconductor Assembly, Testing, Marking and Packaging plant in Gujarat. In other words it's a semiconductor plant.

Now my role is a bit odd. Graduate Engineer Technician (GET). And the pay is 5 LPA (4LPA in hand basic, this is in INR. About 400 usd per month). My interview was a breeze and after about 10 minutes the interviewer basically handed me a role in the factory's Repair Lab. PCB repair, Computer systems repair, semiconductor testing machine repairs, etc.

I have had 2 great internships at the top private and government manufacturing plants in the country and had solid projects that made the interview literally a breeze.

But I know what it's like working at factories. And it's not fun at all. Especially working anywhere near Production (PRD) Lol. It's just too repetitive, product life cycle is too damn long and you are essentially stuck and turn dependent on that plant where you work at and before you relise it, boom you are stuck at that plant, that product and that line. (As in production line).

I was hoping more into R&D or similar stuff. But the company was dead set on the Graduate Engineer "Technician" role.

I have another technical round test for a great Enterprise services company. 9LPA fully remote, night shift US time. But it's yet to be conducted. And as of now I have no leverage to use to try and hike my salary at the semiconductor plant.

It's not exactly bad. But it's on the lower end. Plus I'd be moving about 4 states away to Gujarat on that salary seems a bit of a stretch.

So what should I do? Stick around and experience it for a while - year or 2? Switch? Look for better roles? Etc.

The role is fine, the company name and brand image is fantastic (legit among the best) but the pay is bugging the hell out of me.

I am going into my second year studying engineering in college, and I know that I want to get into the semiconductor industry, but I just don't know what angle I should take. I've narrowed my interests down to Electrical or Chemical Engineering, since I have found equal joy in both chem and circuits classes and I know both majors have paths to semiconductor work.

My question is if the professional work I would do would vary if I pick one over the other and how it would vary. Would one have a more set path?

Any insights I would greatly appreciate.

Hello, I’ll have an interview in the near future for HVM in PE-CVD processes. My question is on what a hiring manager would look in someone with experience in process engineering for thin film deposition but not in a HVM setting. What would bring confidence and reduce the risk for hiring someone on R&D but hands-on process focus.

Hi everyone,

I'm a Materials Science master's student finishing my thesis in about three months, and I'm hoping to start a career in the semiconductor industry.

I have hands-on experience with characterisation techniques such as SEM, XRD, EDX/EDS, and confocal microscopy, along with a solid theoretical background in materials science.

How transferable are these skills to semiconductor roles? Are there any additional techniques, software, or fundamentals (e.g., semiconductor physics, thin films, lithography, cleanroom processes) that I should learn before applying?

I'd appreciate any advice from people working in the industry. Thanks!

I came into this engineering internship excited to learn and contribute. Instead, I left disappointed by what I experienced.

There was virtually no onboarding, no structured training, and no clear technical ownership of my projects. I repeatedly asked for documentation, architecture overviews, or any material that would help me understand the products I was working on, but I was largely told to Google datasheets or find answers on my own.

My manager was new to the technology I was working on, so many of my technical questions couldn’t be answered directly and I was frequently redirected to other engineers. This left me trying to piece together information from different people, many of whom weren’t familiar with my project’s overall goals. Even one week when everyone left for an event , my manger told me to wait until next week when the rest came back to answer my questions. My manger has no experience in the area we are in and seemed to get hired based on knowing a powerful person in group. Add to that people quitting due to the toxic culture and their work getting dumped on the ones left.

My projects had no well-defined specifications or success criteria. Every time I got close to finishing, the scope changed again. It often felt like I was expected to deliver without anyone agreeing on what “done” actually meant.

I consistently asked for feedback because I wanted to improve. Instead, I rarely received direct technical guidance or constructive coaching. I was often left feeling dismissed rather than supported, and some interactions came across to me as intimidating rather than encouraging. That’s not an environment where interns can develop confidence or learn effectively.

Knowledge sharing was inconsistent, and collaboration often felt discouraged. Instead of engineers taking the time to explain design decisions or walk through their reasoning, conversations frequently ended with “that’s wrong” without explaining why. That teaches very little.

This wasn’t my first internship and I am doing my masters, so I have a basis for comparison. In my previous internship, I had clear mentorship, supportive technical leadership, and received two full-time offers after my final presentation. That experience showed me how much good leadership and a healthy engineering culture matter. Looking back , I regret turning down all my other offers for this.

The technology was exciting, but an internship is about more than the product. It’s about mentorship, accountability, communication, and helping the next generation of engineers succeed. Unfortunately, I did not experience those things here.

Cryogenic etching represents the most significant paradigm shift in dielectric etch technology since the transition from wet to dry processing. Driven by the need to etch channel holes exceeding 400 layers in 3D NAND, the industry has converged on a class of process technology that operates at substrate temperatures of negative tens of degrees Celsius — a regime that would have seemed impractical for production dielectric etch a decade ago.

This chapter explains why cryogenic temperature is the enabling variable that makes this class of chemistry work, details the surface reaction mechanisms understood for hydrogen fluoride (HF) based cryogenic etching, examines the two competing technology platforms that have brought cryogenic etching into high-volume production, and assesses the supply chain and environmental implications of this still-rapidly-evolving process category. Readers approaching this chapter after Section 2.6 (gas-phase HF) and Chapter 4 (argon) will find the foundational gas properties already established; this chapter focuses on what changes when these gases are deployed in the cryogenic thermal regime.

A note on sources for this chapter: cryogenic etching is among the newest and most competitively guarded process technologies in semiconductor manufacturing. Tokyo Electron (TEL) has been comparatively open in publishing its underlying chemistry — including HF and phosphorus-containing gas species — through peer-reviewed conference proceedings (AVS, VLSI Symposium). Lam Research, by contrast, has not publicly disclosed the specific gas chemistries used in its Cryo platform; industry reporting confirms only that Lam's three successive cryogenic etch generations have each used different chemistries, without specifying which gases. Where this chapter describes TEL's HF-based chemistry in mechanistic detail, that detail is grounded in TEL's own published technical disclosures. Where Lam's specific chemistry would be required to make an equivalent mechanistic claim, this chapter says so explicitly rather than assuming parity with TEL's disclosed approach.

6.1  Why Temperature Changes Everything

The Limits of Room-Temperature Fluorocarbon Chemistry

The fluorocarbon-based dielectric etch chemistry described in Chapter 2 — C₄F₈, C₄F₆, CHF₃, and related gases — has scaled remarkably well for three decades, but it faces a fundamental physical limit at the aspect ratios now required for advanced 3D NAND structures exceeding 400 layers. As channel hole aspect ratio increases, two related problems intensify: aspect-ratio-dependent etching (ARDE), where etch rate declines as the feature deepens because reactant transport to the bottom of the hole becomes diffusion-limited, and sidewall bowing, where the fluorocarbon passivation layer becomes increasingly difficult to maintain uniformly along the full length of an extremely narrow, deep channel. Patent literature describing cryogenic dielectric etch approaches notes specifically that at cryogenic temperatures, the large fluorocarbon fragments from C₄F₆ and C₄F₈ tend to become stuck near the top of a high-aspect-ratio feature and block the etch front, rather than reaching the bottom — meaning conventional room-temperature fluorocarbon chemistry does not simply transfer to a cryogenic chuck without reformulation.

These problems are not solvable by further fluorocarbon chemistry optimization alone — they are consequences of the fundamental physics of neutral species transport and ion trajectory control in extreme-aspect-ratio features. A different physical regime is required, and cryogenic substrate temperature is the variable that provides it.

Thermodynamics of Surface Adsorption at Cryogenic Temperatures

The behavior that makes cryogenic etching possible is rooted in basic adsorption thermodynamics. The residence time of a gas molecule adsorbed on a surface increases as temperature decreases, following an Arrhenius-type relationship governed by the desorption activation energy. At room temperature, gas-phase HF molecules striking a SiO₂ surface have a short residence time before thermal desorption — as established in Section 2.6, conventional vapor-phase HF (VHF) etching requires a co-reactant (water vapor or methanol) acting as a surface initiator for the HF/SiO₂ reaction to proceed at a useful rate.

At cryogenic substrate temperatures — TEL has disclosed operating in a range of negative tens of degrees Celsius for its production cryogenic etch process — this picture changes. Longer HF surface residence time allows greater surface coverage and reaction time, and patent and conference literature describing cryogenic dielectric etch processes indicate that fluorine sources capable of generating atomic or near-atomic fluorine species — including HF — are favored over large polymerizing fluorocarbon molecules precisely because the small fluorine-bearing species can reach the bottom of an extreme-aspect-ratio feature where the large fluorocarbon fragments cannot.

Suppression of Isotropic Chemical Etching

A second consequence of cryogenic temperature, understood at a general mechanistic level across the cryogenic etch literature, is the suppression of spontaneous, isotropic chemical etching that would otherwise compete with the desired anisotropic, ion-driven etch mechanism. At cryogenic temperatures, the etch chemistry is structured so that material removal proceeds efficiently only where directional ion bombardment activates the surface — at the feature bottom — while the sidewall, shielded from direct ion bombardment, is comparatively protected. The general principle, described in patent literature on cryogenic dielectric etch chemistry, is that different elements serve different roles at cryogenic temperature than they do at room temperature: species effective for etching silicon, oxygen, or nitrogen components of a stack, and species effective as passivating agents, are not always the same as their room-temperature counterparts.

Formation of Stable Passivation Layers on Sidewalls

The third critical temperature-dependent effect concerns sidewall passivation. Conventional room-temperature fluorocarbon processes (Section 2.4) rely on a thick, chemically robust (CF₂)ₙ polymer film to protect sidewalls through mechanical and chemical resistance to lateral fluorine attack. At cryogenic temperatures, a qualitatively different passivation paradigm becomes accessible: species that would be too weakly bound to persist as a stable passivation layer at room temperature can remain adsorbed for the duration of the etch step simply because desorption is thermally suppressed. This is the general mechanism by which TEL's published PHastIE process — Phosphorus and Hydrogen-based Fast Ion Etch — is understood to operate, using a phosphorus-and-hydrogen-containing gas chemistry alongside HF to achieve sidewall protection without the thick polymer films of conventional Bosch-type or HARC processes (Section 2.4).

Comparison with Conventional Fluorocarbon Chemistry

Parameter	Conventional Fluorocarbon (Room Temp.)	Cryogenic Dielectric Etch (General)
Operating temperature	0°C to 60°C	Negative tens of degrees Celsius
Typical fluorine source	C₄F₈, C₄F₆ (large polymerizing fragments)	Small F-bearing species (e.g., HF) favored for bottom-of-feature transport
Sidewall passivation	Thick (CF₂)ₙ polymer film	Thinner, temperature-stabilized passivation layer (chemistry vendor-specific)
Practical aspect ratio target	~40–50:1	3D NAND channel holes for 400+ layer stacks
ARDE sensitivity	High at extreme AR	Reduced — primary value proposition of the technology

Table 6.1  General comparison of conventional room-temperature fluorocarbon etching and cryogenic dielectric etching

Section Notes

1  U.S. Patent Application 2023/0187234, Plasma Etching Chemistries of High Aspect Ratio Features in Dielectrics, Lam Research Corporation.

2  U.S. Patent Application 2021/0005472, Plasma Etching Chemistries of High Aspect Ratio Features in Dielectrics, Lam Research Corporation.

3  Tokyo Electron Ltd. Cryogenic Etching — Tokyo Electron's Digital and Green Transformation of Semiconductor Process Equipment. Company blog, October 2024.

More content please you click link as below

https://a.co/d/09sYYkPy

Across all the internet platforms people always complain about TSMC salary is it really bad though? How much does TSMC process engineer, r&d engineer earn in NTD? Are they satisfied or not?

I just gave a final round interview with micron and the legal team BAL reached out for immigration docs and the very next day I get a rejection email from the HR.

Is it because of documents or last minute internal hire ? Is this common in micron ?

It was for a new grad role and I am an f1 student.

Hey r/Semiconductors,

Over the past few years, I’ve noticed a gap in structured, practical resources detailing the complex world of etching gases C4F6，CF4，HCl, Cryogenic etch...and their specific behaviors in RIE/ICP systems.

To bridge this gap, I’ve compiled my industry experience into a book that is now officially available on Amazon. It covers:

• Detailed chemical properties and reaction mechanisms of core etching gases.
• Process optimization strategies for different substrates (Silicon, Dioxide, Nitride).
• Crucial safety protocols, abatement methods, and gas delivery system design.

Whether you are a process engineer, a student entering the fab, or working in facility safety, this guide is built to be a practical reference.

Check it out on Amazon if you're interested! (Search for [Etching Gases in Semiconductor)

https://a.co/d/01wVHwWd

Would love to hear any feedback or answer any questions here.

Anyone ever done traveling FSE role for Applied Materials? Good perks? Per diem, schedule on the road?

​

Hi everyone,

We are running a community of students who are learning about or just entering the semiconductor industry. Our mission is to help students become industry-ready through practical, real-world learning.

We're looking for:

• PhD holders in semiconductor-related fields

• Semiconductor industry professionals

• Engineers with real-world experience who are interested in mentoring students

We're planning to organize masterclasses, expert talks, mentorship sessions, and hands-on learning experiences to help students understand how the semiconductor industry actually works beyond textbooks.

If you're interested in mentoring, delivering guest lectures, or sharing your industry experience with aspiring semiconductor engineers, please send me a DM. We'd love to collaborate and help shape the next generation of semiconductor professionals.

Base:£70,000/-
Bonus:£14,000/-
RSU:30,000/- per annum..
I have 11 yrs of experience?
Did they lowball? Or what is your views?

New grad deciding between two hardware/silicon offers and would appreciate advice.

Offers:
Apple — hardware/silicon role — Austin
NVIDIA — hardware/silicon role — Bay Area
Financially, Apple looks stronger for me. The equity grant is significantly higher, Austin is much cheaper, there’s no state income tax, and I’d likely save more month to month. NVIDIA has higher base/sign-on, but the smaller equity grant plus Bay Area taxes and cost of living make the overall financial picture less attractive.

Apple:
Much better financial comfort
Larger equity grant
Lower cost of living
Better monthly savings
Concern: unsure about long-term growth, refreshers, and team mobility

NVIDIA:
Stronger AI/semiconductor momentum
Potentially higher stock upside
Very strong brand in the current market
Concern: smaller equity grant, higher COL/taxes, and less monthly savings

I’m leaning Apple financially, but NVIDIA’s long-term upside and technical reputation are making the decision harder.
For people in hardware/silicon or anyone who has worked at either company: would NVIDIA’s growth/brand be worth giving up the better financial setup at Apple, or is Apple the smarter new grad choice here?

Hi everyone,
I’m trying to understand the semiconductor industry from a business perspective, not just the technology.
If someone wanted to build a semiconductor-related business from scratch in any country, what would the roadmap look like from 0 to 100?
I’m looking for a complete overview, including questions like:
What are all the different types of semiconductor businesses?
Which businesses require low investment, medium investment, and very high investment?
What parts of the supply chain can a startup realistically enter?
Which businesses are service-based, manufacturing-based, design-based, or trading/distribution-based?
How does the semiconductor ecosystem work from raw materials to the final chip?
Which sectors have the highest growth potential over the next 10–20 years?
If you were starting today with limited capital, where would you begin?
What skills, certifications, equipment, and partnerships are essential?
What common mistakes do first-time founders make?
I’m not specifically interested in building a billion-dollar chip fabrication plant. I want to understand every possible business opportunity in this industry—from small businesses that can be started with limited capital to large-scale ventures.
If you work in semiconductors or have experience in the industry, I’d really appreciate your insights, recommended books, YouTube channels, courses, or any roadmap that helped you understand the ecosystem.
Thank you!

I saw a posting for this, and applied, but I never got an interview. I was wondering if interviews are reserved for people with Master's and PhD degrees, with 10+ YOE. Or do I just need prior experience, relevant to microLEDs? It looked very competitive to get, LinkedIn showed that over 100+ people applied.

For reference, I have a Bachelor's in Chemical Engineering, and only have 7 YOE.

I have a MSc. in Physics. Worked in simulation, design, layout, and characterization of Rapid Single Flux Quantum (RSFQ) electronics, and want to join the semiconductor industry in doing something similar (simulation, design, layout, and testing).

Since my background is in experimental physics, I want to know which skills are most fundamental to landing a job in the semiconductor field.

Hi everyone,

I don’t usually post like this, but I’m honestly in a tough situation and trying my best to find a new grad opportunity in the U.S.

I graduated in Dec 2025 with an MS in Computer Engineering from a public university in the Bay Area, with a 3.83 GPA. My main focus was computer architecture, embedded systems, microprocessor design, advanced computer design, and hardware/software integration.

I’m looking for new grad / entry-level roles in Design Verification, Validation, Embedded Software, Firmware, Systems/Platform Software, or SoC-related roles.

My skills include C, C++, Python, embedded C, Verilog/SystemVerilog basics, FPGA/Vivado, Linux debugging, scripting, memory-mapped register validation, and hardware/software debugging.

I have 6 months of software engineering internship experience and also worked as a TA/Instructional Student Assistant for multiple computer engineering courses, where I helped students with labs, debugging, and grading.

I did get good interview opportunities with companies like Amazon Annapurna, NVIDIA, ARM, and Qualcomm, but due to headcount/timing/final-round outcomes, nothing converted. I’m still preparing seriously and I’m interview-ready. I can do Blind 75 / LeetCode 150-style coding interviews and can interview remote or onsite.

I’m authorized to work in the U.S. and open to relocate.

If anyone knows any recruiter, hiring manager, referral, or opening for DV / validation / embedded / firmware / systems roles, please let me know. I would genuinely be grateful for any help.

Resume available on request. Thank you for reading.

Hey r/Semiconductors,

I'm an independent researcher from Hyderabad, India working on Project Topo-RF - a passive RF metamaterial structure targeting 5 GHz (S-Band/C-Band).

What it is:
A 10,000-node capacitively-coupled gold resonator mesh on a high-resistivity quartz substrate. 100×100 grid, 150µm pitch, 5-10µm inter-node gaps. The goal is to characterize group delay and dispersion behavior of this topological mesh vs. classical sequential transmission lines.

Current status:

• GDSII layout file ready (project_topo_rf_phase0_2port.gds)
• Full fabrication SOP ready (LOR+S1813 lift-off, Ti 5nm + Au 200nm, e-beam evaporation, Class 1000 cleanroom)
• Looking for cleanroom access in India (exploring IIIT-H FabLab and IIT Hyderabad)

Asking for:

1. Anyone with experience accessing university fabs in India as an external/independent researcher - what was your process?
2. RF engineers or researchers interested in collaborating on this project
3. Any technical feedback on the approach

Happy to share the engineering docs with anyone interested. DM open.