
After years in Design Verification, I finally started the YouTube channel I wish I had as a beginner
Hi everyone! I’m a Design Verification engineer and recently started a YouTube channel where I explain SystemVerilog, UVM and DV interview topics in a practical way.
I’m looking for honest feedback from the community and suggestions for future videos.
https://youtube.com/@dv_street
Thanks!
u/Rishi_Muni_1608 — 9 days ago