Is RV32I still worth doing as a final year project for RTL roles?
Hey guys,
I’m a final year student aiming for RTL design roles. I was thinking of building a 32-bit RISC-V (RV32I) core from scratch as my final year project.
But is a basic RV32I core still relevant in 2026, or is it too common now?
Should I instead add something interesting like pipeline, cache, branch prediction, custom instructions, formal verification, etc. Or maybe do something completely new with RISC-V?
If you were in my place, what kind of project would you build to actually stand out for an entry-level RTL role?
Any suggestions from people working in RTL/ASIC/FPGA would be really helpful :)