I am 2026 graduate from an IIT, I worked in the field of Non volatile memories and published two papers. I am seeking full time roles in Memory circuit design roles. Have know both analog and digital circuits and device physics concepts. If anyone working in memory design companies or related roles could you plz provide a referral?
So i completed my 1st year (ece branch) and still very lost about what skills to learn & where to start from, so i have been searching a lot on youtube , google, seeing profiles of ece graduates on linkedin to figure out what to do but still i have no clear idea in my head
Then i came across this roadmap on github which i felt cleared my head and gives a straightforward direction , please suggest should i follow it ?
Hey, my cgpa is low 5.5, i have got iit kanpur vlsi Branch but I really fear that my ug cgpa will affect my placement.
Can someone please guide me on this
Can anyone guide me on IP Design role what are the roadmap to learn and with 1 or 1.5 yrs exp can I switch to product based companies? I need an idea how to productively learn handson
I am attaching my resume, please help me out here.
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Hi everyone,
I am a 2026 B.Tech graduate from a Tier-3 college. I recently received an offer from Siliconus for a Physical Design role, and I have a few questions for people who have joined or know about the company.
Has anyone received their joining letter or joining date for the 2026 batch? If yes, when did you receive it?
The company has a 4-year service bond. The salary structure is:
- First 2 years: around 4 LPA
- Third year: 20–50% performance-based hike
- Fourth year: no fixed limit on the hike (performance-based)
For someone starting their career, is signing a 4-year bond worth it?
I know the semiconductor market is improving, but a 4-year commitment feels like a big decision. My concern is whether I should join Siliconus and gain Physical Design experience, or continue preparing and wait for better opportunities.
If you were in my position—a 2026 graduate from a Tier-3 college—what would you do in the current market? I would really appreciate advice from people working in VLSI or who have experience with Siliconus.
Thanks in advance.
If the btech CGPA matters, how much i cgpa in UG is safe in vlsi companies like nvidia, Qualcomm,intel and so on.
Currently I am in a waiting list for one of the colleges and I want to study ece ( still in waiting)as my subject but I have got VLSI people are saying that VLSI is a course in ece. But as everyone right now is more inclined towards the ECE subject please anyone with a knowledge please tell me what should I take ,is VLSI having a future and where would I be after completing the course.
Im actively searching for internship/apprenticeship
So far applied in
Qualcomm
Infineon
GlobalFoundaries
Synopsys
Micron
Mediatek
And many more can't even remeber
Not even getting an interview call. Whare am I going wrong ?
Is it the CGPA ?
Really feeling worthless now and getting panic attacks every night before sleeping and after waking up
Any senior please help
I just an admission into NITH MTech VLSI. How is the placement there
I’ve applied to 100+ internships and entry-level VLSI/ASIC roles over the past few months with this resume, but I’m barely getting any interviews.
I’m a 2026 ECE graduate targeting:
ASIC Physical Design
Digital Design
SoC/Physical Design Engineer roles
Please roast it brutally. Don’t hold back.
I’m not looking for compliments—I want honest feedback.
Some questions I have:
What’s the biggest red flag?
What would make you reject it in 10 seconds?
Is it too crowded or difficult to scan?
Are the projects weak or just presented poorly?
Does it sound like I only followed tutorials?
What would you remove or rewrite?
If you were a recruiter or hiring manager, would you shortlist me? If not, why?
I’ve already revised this resume multiple times, so I’m hoping for fresh perspectives.
Any advice from recruiters, hiring managers, or VLSI engineers would be greatly appreciated. Thanks!
Hey everyone,
I am working on an IC layout and running into some annoying LVS issues after switching from a MIMCAP to an NMOS capacitor.
When I use a MIMCAP, everything passes LVS without any issues. But as soon as I try to use an NMOS cap instead, the LVS report throws a bunch of device mismatches, net mismatches, and rewiring errors.
I know that MIMCAPs sit high up in the metal stack and are isolated, while NMOS caps sit right in the substrate. I am guessing my issue is coming from how I am handling the bulk connection or how I am tying the terminals together, but I can not seem to spot the exact mistake.
Do I need to explicitly route a guard ring/substrate tap to the Source/Drain metal connection right at the device level? Also, how do you usually structure multi-finger MOSCAPs in the schematic versus the layout to avoid width and length extraction errors?
While using big capacitors and transistors, some times even with maximum limit of length and width of transistors and caps we can't meet the design requirement...does putting multiplier help? or should i have to place one more identical design to meet the requirement (this is particularly in schematics)?
On a related note, I wanted to ask about the design trade-offs here. I know MOSCAPs have much better area density, but it is the voltage-dependent non-linearity of this cap concerns me.
i am using GPDK 90nm i am still in my UG, i don't have access to industry level PDK's as of now. I have used nmoscap_1v from GPDK 90nm, i am trying to do a miller compensated OTA.
Would appreciate any insights or debugging tips on this. Thanks!
Hi everyone,
I have an upcoming interview this Monday for an AMS Verification role at a product-based semiconductor company. I wanted to ask the community what you think are the must-know topics or concepts that I should know before the interview.
Any suggestions, interview experiences, or last-minute tips would be greatly appreciated. Thanks in advance!
I’m trying to finalize my CCMT choice between NIT Rourkela (M.Tech VLSI Design & Embedded Systems) and NIT Kurukshetra (M.Tech VLSI Design).
I’m looking for inputs specifically from current students, alumni, or people who have interacted with these departments.
I’d appreciate comparisons on:
1. Placements (2024–2026 preferred)
● Core VLSI companies visiting (Qualcomm, Synopsys, AMD, Intel, TI, NXP, MediaTek, etc.)
● Internship and PPO opportunities
2. Academics
● Course structure
● Faculty quality
● Research culture
● Ease of maintaining CGPA
3. Labs & Infrastructure
● EDA tools (Cadence, Synopsys, Mentor, etc.)
● Lab quality
● Computing resources
4. Industry Exposure
● MoUs with semiconductor companies
● Sponsored projects
● Alumni network in VLSI
5. Campus Life
● Hostel and mess
● Student clubs
● Overall environment
● City and connectivity
6. Overall ROI
If you had these two options today, which one would you choose, and why?
I’m only comparing these two institutes, so I’d prefer comments focused on this comparison.
Whats I have researched is: NIT KKR have good internships. And avg/median packages hover around 23~24LPA. Whereas NIT Rourkela have better brand name TIER-1, TOP-4 NIT. And good “ECE” median packages, sole VLSI isn’t stated.
Thanks in advance!
As the title says. Applied back in april, may and june for the position: Interim Engineering Intern_Systems- 2026 and JOB ID: 3089963 and position: Interim Engineering Intern (1 Year)- Hardware JOB ID: 3086709
haven't hear anything ever since neither you have been "REJECTED" nor you have been "SELECTED".
if anyone seeing this from Qualcomm atleast if not rights, you should have courtesy to tell an applicant that you haven't been selected. its really painful to keep up with he hope that i might have a chance.
I am seeing a dangerous situation happening in the tech industry, especially in VLSI. Many companies have stopped hiring freshers, and many AI silicon startups are hiring only for senior-level positions (5-10 yoe). This means in the near future, we might have fewer qualified engineers. Is this situation fine? I think companies are trying to push AI too hard without preparing the next generation. Placing a huge bet on AI. Hope it won't destroy the industry.