Struggling with LVS errors (device/net mismatch) on NMOS Cap layout – works fine with MIMCAP. Help?
Hey everyone,
I am working on an IC layout and running into some annoying LVS issues after switching from a MIMCAP to an NMOS capacitor.
When I use a MIMCAP, everything passes LVS without any issues. But as soon as I try to use an NMOS cap instead, the LVS report throws a bunch of device mismatches, net mismatches, and rewiring errors.
I know that MIMCAPs sit high up in the metal stack and are isolated, while NMOS caps sit right in the substrate. I am guessing my issue is coming from how I am handling the bulk connection or how I am tying the terminals together, but I can not seem to spot the exact mistake.
Do I need to explicitly route a guard ring/substrate tap to the Source/Drain metal connection right at the device level? Also, how do you usually structure multi-finger MOSCAPs in the schematic versus the layout to avoid width and length extraction errors?
While using big capacitors and transistors, some times even with maximum limit of length and width of transistors and caps we can't meet the design requirement...does putting multiplier help? or should i have to place one more identical design to meet the requirement (this is particularly in schematics)?
On a related note, I wanted to ask about the design trade-offs here. I know MOSCAPs have much better area density, but it is the voltage-dependent non-linearity of this cap concerns me.
i am using GPDK 90nm i am still in my UG, i don't have access to industry level PDK's as of now. I have used nmoscap_1v from GPDK 90nm, i am trying to do a miller compensated OTA.
Would appreciate any insights or debugging tips on this. Thanks!