Unless your profit is measured in a few cents per unit sold in the millions, every USB Type C shield should be separated from logic GND by a 4.7nF 50V cap and a 1M ohm resistor in parallel going into a ferrite 600Ω@100MHz, so there is a RC network connected to ferrite between shield and GND. At the very least it prevents you from having the shield tied directly to your GND plane. sure call the ferrite optional but its pretty cheap insurance. Unless you know from rigorous testing these are not needed, but its a very sound approach. At the very least it forces you to have the footprints and then you could put 0ohm resistors in place. But, if you don't have a EMC compliance testing system or are building boards and then plan on doing compliance testing, this is very inexpensive insurance. Also TVSs on the USB signals. "Oh but i'm just prototyping - yea well plan for success". its currently the number #1 error this week that I find. maybe some would argue its not an "error". but isn't it a "I get by" at best?

A small snippet of  https://github.com/phenax/sinthinator a musical instrument using capacitive touch, PCB design review and quality check. its a really interesting idea. Potentially it could play "Good vibrations"?

https://tomachie.com/r/201dd1be-4a04-48ec-962d-3ddfc2eaa1c5/sinthinator_report.html

Small designs, 2 pages or less for students and hobbyist are totally free. I'd rather have you just upload your design than me downloading from github and then uploading to Tomachie.

This design has two external connectors: J2, a USB Type-C receptacle used for USB 2.0 data and 5V power input, and J1, a 3.5mm TRRS audio jack driven by the PAM8302A Class-D mono audio amplifier (U8). The board is powered from the USB VBUS rail through an AMS1117-3.3 linear regulator (U7), producing a single 3.3V domain that supplies all active ICs. There is a single ground domain (GND) with no separate chassis ground plane or dedicated EMC barrier visible in the schematic.

The USB-C connector J2 has its SHIELD pin and GND pin connected together on the net Net-(J2-GND). This net is isolated from the main board GND rail. The connector shell and signal ground are tied together, but neither is connected to the board-level GND plane through any filtering or direct connection visible in the schematic. This creates a floating shield condition: the connector metalwork and cable shield are not referenced to the PCB ground plane. In a product without a metal enclosure, this means the cable shield cannot serve as an effective EMI return path, and ESD energy arriving on the connector shell has no defined discharge path to the board ground. The likely in-field failure mode is ESD coupling into signal traces during contact discharge events (per IEC 61000-4-2), and degraded common-mode noise rejection on the USB data lines leading to radiated emissions failures against CISPR 32 / FCC Part 15 Class B limits.

For the audio output path, U8 (PAM8302A) drives J1 directly on nets Net-(U8-OUT+) and Net-(U8-OUT-) with no series ferrite beads, no EMI filter, and no output capacitors between the amplifier outputs and the TRRS jack. The PAM8302A is a filterless Class-D amplifier that produces a PWM switching waveform at approximately 250 kHz on its output pins. Per the PAM8302A datasheet (DS41333 Rev. 6, Diodes Inc.), most applications require a ferrite bead filter on the output, and the datasheet states that the ferrite filter suppresses EMI at approximately 1 MHz and above. Without any output filtering, the high-frequency PWM content will radiate from the headphone cable acting as an antenna. The likely failure mode is radiated emissions in the 1 MHz to 30 MHz range, which would cause non-compliance with CISPR 32 / EN 55032 Class B and FCC Part 15 Subpart B. Additionally, conducted emissions on the headphone cable may couple into other equipment.

12.1.2 J2 — USB Type-C Receptacle: ESD and EMC Assessment

AI-Assisted J2 is a USB 2.0-only Type-C receptacle in a right-angle SMD footprint. This is a consumer-facing, externally accessible connector subject to frequent hot-plug events and direct human contact. Per IEC 61000-4-2, consumer-facing ports are expected to withstand at least Level 4 contact discharge (8 kV contact, 15 kV air). USB Type-C connectors are particularly vulnerable due to their tightly packed pin pitch, which increases the risk of ESD coupling between adjacent pins.

The schematic shows no TVS or ESD protection diodes on any of the USB signal lines. The D+ and D- data lines (nets Net-(J2-D+) and Net-(J2-D-)) connect directly from the J2 connector pins to the board with no intermediate protection. These nets connect A6 to B6 and A7 to B7 respectively, but no downstream IC connection is visible on these nets in the provided schematic data, and no TVS device is present. The CC1 and CC2 configuration channel lines (nets Net-(J2-CC1) and Net-(J2-CC2)) each connect through a 5.1k pull-down resistor (R10 and R11 respectively) to GND, which is the correct USB Type-C sink identification per the USB Type-C specification. However, these lines also lack any ESD protection. The VBUS line (+5V) connects through a 10uF tantalum capacitor (C3) to GND and feeds U7 pin VI, again with no TVS clamping device.

The connector shield (J2 pin S, SHIELD) and connector ground (J2 pin GND) are tied together on net Net-(J2-GND), but this net does not connect to the board GND rail. This is a significant EMC concern. Per Intel EMI Design Guidelines for USB Components and Silicon Labs AN0046, the USB connector shell should be connected to the PCB ground plane, either directly or through an RC filter (typically a 4.7nF capacitor in parallel with a 1M ohm resistor), to provide a defined ESD discharge path and EMI shielding return. The current floating-shield topology means ESD energy on the connector shell has no path to ground, and the cable shield cannot function as an EMI barrier. The likely failure modes are ESD-induced latch-up or damage to downstream ICs, and radiated emissions from the unshielded USB cable acting as an antenna.

Investigation of TVS protection on the D+, D-, CC1, CC2, and VBUS lines is warranted. For USB 2.0 data lines, low-capacitance bidirectional TVS diodes (typically less than 1 pF, rated to IEC 61000-4-2 Level 4 or above) are standard industry practice. For CC lines, higher-capacitance protection is acceptable since these are low-speed signals. For VBUS, a unidirectional TVS rated for the 5V working voltage is typical.

12.1.3 J1 — 3.5mm TRRS Audio Jack: ESD and EMC Assessment

AI-Assisted J1 is a 3.5mm TRRS audio jack in a right-angle SMD footprint, indicating panel-mount or external access. This is a consumer-facing connector where users will frequently insert and remove headphone or audio plugs. The insertion of a charged plug generates ESD events, and the headphone cable acts as an antenna for both radiated emissions pickup and emission of noise from the Class-D amplifier output.

The PAM8302A outputs (U8 pin 5 OUT+ and pin 8 OUT-) connect directly to J1 with no intervening components. Net Net-(U8-OUT+) connects to J1 pins R1 and T, and net Net-(U8-OUT-) connects to J1 pins R2 and S. There are no TVS diodes, no ferrite beads, and no series resistors on these output lines. The PAM8302A datasheet (DS41333 Rev. 6) does not specify on-chip system-level ESD protection to IEC 61000-4-2 levels. The device has internal short-circuit and thermal protection, but these are not ESD protection mechanisms.

Per TI System-Level ESD Protection Guide (SSZB130), audio jacks are entry points for ESD, and bidirectional TVS diodes rated to IEC 61000-4-2 Level 4 are recommended on audio lines. Since audio signals do not exceed 30 kHz, TVS capacitance is not a signal-integrity concern for this interface. The absence of any ESD protection between J1 and U8 means that an ESD event on the headphone plug will propagate directly into the amplifier output stage. The likely failure mode is damage to the U8 output FETs or latch-up of the amplifier.

Additionally, the PAM8302A IN- pin (pin 4) is tied to GND, and IN+ (pin 3) is driven from U3 (a DAC or signal source) on net Net-(U3-VOUT). The ~{SD} shutdown pin (pin 1) is pulled up through R6 to 3.3V. The amplifier is in a single-ended input configuration. No input-side filtering or protection is present, but since the input is not connected to an external connector, this is less of an ESD concern.

From an EMC perspective, the absence of ferrite beads on the Class-D output is the primary concern. The PAM8302A switching frequency is approximately 250 kHz, and harmonics extend well into the MHz range. The headphone cable connected to J1 will radiate these harmonics. The PAM8302A datasheet explicitly recommends ferrite bead filters on the output for most applications. Without them, the design is at high risk of failing radiated emissions testing per CISPR 32 / EN 55032 / FCC Part 15.

12.1.4 Observations and Findings

AI-Assisted The design has two consumer-facing connectors (J1 and J2), both accessible to end users and both lacking ESD protection devices. The ground architecture uses a single GND domain with no chassis ground separation, which is acceptable for a small, unshielded portable device, but the USB-C connector shield is not connected to this ground domain, creating a gap in the EMC strategy.

The USB-C connector J2 has its shield and ground pins on an isolated net (Net-(J2-GND)) that does not connect to the board GND plane. This must be addressed: the shield should connect to GND either directly or through an appropriate filter network. Without this connection, the design will likely fail both ESD immunity testing (IEC 61000-4-2) and radiated emissions testing (CISPR 32).

The Class-D amplifier output to J1 lacks the ferrite bead EMI filter recommended by the PAM8302A datasheet. This is a radiated emissions risk that will be difficult to mitigate after layout. Ferrite beads should be placed in series with each output line (OUT+ and OUT-) as close to U8 as possible, with small capacitors (typically 220pF to 1nF) from each filtered output to GND.

The 5.1k CC pull-down resistors R10 and R11 correctly identify the port as a USB Type-C sink per the USB Type-C Cable and Connector Specification. The 10uF tantalum capacitor C3 on VBUS provides bulk decoupling but does not substitute for transient voltage suppression.

Power supply decoupling for U8 is provided by the shared 3.3V rail capacitor bank, which includes multiple 100nF and 10uF capacitors. The PAM8302A datasheet recommends a 1uF ceramic close to VDD and a 10uF or larger for low-frequency filtering, and these values are present in the design. However, the decoupling capacitors listed appear to be shared across the entire 3.3V rail rather than dedicated to U8, so placement proximity during layout will be critical for audio performance and PSRR.

https://tomachie.com/r/201dd1be-4a04-48ec-962d-3ddfc2eaa1c5/sinthinator_report.html#emc_checks

Connector	Finding	Risk
J2 (USB-C)	Connector shield pin (S) and GND pin are on isolated net Net-(J2-GND) with no connection to board GND plane. Cable shield has no defined return path. Likely failure: radiated emissions non-compliance (CISPR 32 / FCC Part 15) and ESD susceptibility (IEC 61000-4-2). Per Intel EMI Design Guidelines for USB Components, shield should connect to ground plane directly or via RC filter.	High
J2 (USB-C)	No TVS or ESD protection on D+ / D- data lines (nets Net-(J2-D+), Net-(J2-D-)). These are consumer-facing hot-plug lines exposed to contact and air discharge per IEC 61000-4-2. Industry practice per USB Type-C design guidelines recommends low-capacitance TVS diodes on USB 2.0 data lines. Investigation warranted.	Medium
J2 (USB-C)	No TVS or ESD protection on CC1 / CC2 configuration channel lines (nets Net-(J2-CC1), Net-(J2-CC2)). CC pins are adjacent to VBUS in the Type-C connector and exposed to cross-pin ESD coupling. Per Semtech USB Type-C ESD application guidance, discrete TVS diodes are recommended on CC lines. Investigation warranted.	Medium
J2 (USB-C)	No TVS protection on VBUS (+5V) power input line. A unidirectional TVS rated for 5V working voltage is standard practice for USB power input protection per IEC 61000-4-2 and IEC 61000-4-5. Investigation warranted.	Medium
J2 (USB-C)	CC1 and CC2 pull-down resistors R10 and R11 (5.1k each to GND) correctly identify the port as a USB Type-C current sink per USB Type-C Cable and Connector Specification Rev. 2.1. No issue.
J2 (USB-C)	VBUS bulk decoupling capacitor C3 (10uF tantalum) is present between +5V and GND. Adequate for input power filtering per AMS1117-3.3 datasheet requirements.
J1 (3.5mm TRRS)	No ferrite bead EMI filter on PAM8302A Class-D output lines Net-(U8-OUT+) and Net-(U8-OUT-) between U8 and J1. PAM8302A datasheet DS41333 Rev. 6 (Diodes Inc.) states most applications require a ferrite bead filter to suppress EMI at 1 MHz and above. Headphone cable will act as antenna for PWM harmonics. Likely failure: radiated emissions non-compliance with CISPR 32 / EN 55032 / FCC Part 15 Class B.	High
J1 (3.5mm TRRS)	No TVS or ESD protection on audio output lines between U8 and J1. The 3.5mm jack is consumer-facing and subject to charged-plug insertion ESD events. Per TI System-Level ESD Protection Guide (SSZB130), bidirectional TVS diodes rated to IEC 61000-4-2 Level 4 are recommended on audio jack lines. Investigation warranted.	Medium
J1 (3.5mm TRRS)	PAM8302A output pins (OUT+, OUT-) connect directly to J1 with no series resistance or current limiting. PAM8302A has internal short-circuit and thermal protection per DS41333 Rev. 6. Acceptable for speaker drive but provides no system-level ESD mitigation.	Low

Headline is wrong, this is a RC Controller, not a flight conroller. thans for the correction r/010010 https://www.reddit.com/user/O1OO1O/ posted for a PCB Design Review and shared his files on github https://github.com/alx-uta/Orthrus-TX/tree/dev/PCB

A number of concerns were raised, the limitation of the 600ma LDO for instance. more attention to the caps needed and the usual issues where type-C shell is not separated from logic GND. Good design has room for improvement. I ran with typical lab setup so limited test points inserted.

Device	Rail / Net	Observation	Severity
LD1 (AP2112K-3.3)	LD1_3.3v	Output rail supplies the entire STM32H745ZIT6 digital domain, SD card, six ESD arrays, and dozens of pull-up resistors. Aggregate load can approach or exceed the 600 mA rating of the AP2112K-3.3 (DS39724 Rev. 2-2). Thermal dissipation in SOT-23-5 at worst-case headroom is a concern.	High
STM32H745ZIT6	VCAP	VFBSMPS (pin 17) output capacitor C22 is 4.7 uF. AN4938 Rev 7 (ST) specifies 10 uF minimum with 20 mohm ESR on this node. Insufficient capacitance risks excessive VCORE ripple and SMPS instability.	High
STM32H745ZIT6	VLXSMPS	AN4938 Rev 7 specifies a 220 pF capacitor between VLXSMPS and GND. No such capacitor is present on the VLXSMPS net. Missing snubber increases switch-node ringing and EMI.	High

The full review is here: https://tomachie.com/r/aa8d1d40-a3e4-499e-a949-0faa610402b9/Orthrus-TX_report.html

While my friend Dr. Alex Zhavoronkov is in a very different field, building tools that use AI for drug discovery, his insight after reading "Open to Work" is applicable to PCB schematic capture and design. You may know Roslansky from Microsoft and Raman from LinkedIn. These are quality men with good vision and pulse on industry. and the message is clear, AI won't replace human work, it will AMPLIFY the parts that matter. (Something i have said as well. I receive no money and have no interest in the royalties generated from this book. I am sharing MHO on technology useful to our field) The future belongs to those who combine AI tools with human strengths, judgement, creativity, adaptation, leaving AI to do rudimentary parts, checking construction, noise, EMC, IPC/IEEE/IEC/ISO/CISPER compliance that is very hard for us to remember all the rules on.

Be vary wary of those quick to vote down anything related to PCB Design and AI as "AI Slop". While there is one particular "fluxing" PCB design tool which is buggy and takes on too much with little results, don't throw out the baby with the bath water or you will find yourself jobless. and maybe there are some DIY solutions which are problematic, having hallucinations and other effects, still that does not mean AI can't help. There's even a sub-Reddit r/PrintedCircuitBoard which prevents the discussion of AI, and i think that is unfortunate for a lot of young designers.

Where AI can free you to do other human things, like create, its would be useful to have as a partner in your PCB design journey. Major OEMs are embracing it, given the risks/costs associated with designs which have mistakes or compliance issues. Stay open minded.

https://preview.redd.it/73rerplzr42h1.png?width=961&format=png&auto=webp&s=c8129c6e4baa182ea932a5aa9276c2398f2881c0

or Rooms? or just a sheet dedicated to the EMC shielded area? I've seen just polygons used to communicate "doghouse" or "tin can" or "shielded", was trying to move towards something more formalized. Dashed box with EMC shield seems to work as then you can have an impedance blanket inside of that. Others have suggested put it on a sheet by itself and add freeform text. To be clear, I'm interested in communicating the design intent in the schematic, much like one would use a Chassis GND symbol, not wait for layout.

I see request for review of schematics on r/PrintedCircuitBoard r/kicad, r/altium , and I get schematics to review and I will see deviations from IEEE 315/ ANSI Y32.2. Is there a reason designers have that they cannot or will not follow ANSI Y32.2? I sometimes see IC# for refdes instead of U#. CN# for connectors in Asia, sometimes. I see where IEC 81346 could come into the situation where someone has industrial training, so they want to use K# for the processor, but that standard is for plant documentation, not for PCB schematics. I am not seeing a international standard in Europe or Asia which competes wiht ANSI Y32.2/IEEE 315. It would be interesting if in these groups where a review is asked for that it meet IEEE 315. What do you all think? is it practical? correct? Is this a good foundation to teach students and new designers using r/Kicad or r/Altium and other EDA tools? TIA

For board-level work, IEEE 315 conventions have some real advantages worth weighing:

• Tool alignment — EDA libraries, schematic linters, BOM generators, and ECAD-MCAD bridges are built around these conventions
• Vendor consistency — IC manufacturer reference designs use them across regions
• Readability across teams — a designer in Taipei, Stuttgart, or Austin can pick up the schematic and know R10 is a resistor without consulting the BOM
• AI and automation compatibility — automated tools expect schematic data in certain standard ways, IEEE 315, IEEE 1149.1, IPC 7351B etc to classify components correctly

For systems-level work — control cabinets, plant integration, machinery documentation — IEC 81346 serves its purpose well but it wasn't intended for PCB electrical schematics.

A working refdes set for PCB schematics from IEEE 315

Component	Refdes
Resistor	R
Capacitor	C
Inductor	L
Diode (any kind, including LED)	D
Transistor	Q
Integrated circuit (any kind)	U
Crystal / oscillator	Y
Fuse	F
Connector (jack / plug)	J / P
Switch	S
Transformer	T
Relay	K
Battery	BT
Test point	TP
Antenna	E
Ferrite bead	FB

Aware of legacy CR-for-diode and X-for-crystal variants from mil-aero work — those have their own context and history.