Hey all, a review for this project would mean the world to me.

The board is designed to hold a soft-core 6502 microprocessor, with plenty of peripherals to mess around with. The BIOS/code for the MCU will be appended above the FPGA config bitstream. The iCE40HX4k is capable of running USB with the nand2mario project, and it also has VGA and HDMI video output. I have used USB-C with a power-negotiation chip to deliver up to 10W, alongside a TPS54386 dual buck converter for deriving the 3.3V and 1.2V power supplies. I also use a diode to get 2.5V since it's flexible unlike the 1.2V supply. PS/2 uses level shifters to translate the 5V bus to 3.3V for the FPGA. I'm also using a 4M x 4B x 16Bit SDRAM for the on-board memory.

I've done my best to follow datasheets and best practices. Feel free to be picky with your review, and tell me anything that might need to get changed.

Thanks!

Hello All,

For those new to KiCad a great example design out there is the CERN White Rabbit VME WREN design. its 73 pages with hierarchy, FPGA and robust power system that is worth looking at to understand the power of KiCad and also give tips on how to design a complex power system for an FPGA.

The WREN (White Rabbit Event Node) is designed in multiple form factors including VME64x, this design is the VME version. It's based on the Zynq UltraScale+ SoC and licensed under the CERN Open Hardware License. White Rabit provides timing in the low 10s of picoseconds for the LHC. I can't say i know all about it but it is quite an acheivement. The original files are here:
https://gitlab.com/kicad/code/kicad/-/tree/5371312c6f945e99bd464769626d83c7111f18ed/demos/vme-wren

I inserted test points and generated descriptions of the power and EMC/ESD sections which may help anyone who is debugging the boards or looking to understand the design. There are some comments on things which are marginal or could be done better in a next generation. The new files are here:

https://github.com/ttrain4086-cpu/Kicad-VME-Wren-Update

There are areas of concern with TPS62125, and the PGOOD status is not always brought out to a probable test point such that debug could be a little easier when things go wrong. Here is a short description of the power, for brevity just 1 section of the entire 14 section power description:

The design is a VME-format board built around a Xilinx Zynq UltraScale+ XCZU4CG FPGA (IC14). Two independent backplane power domains feed the board. The P12V rail enters from the VME P1 connector and supplies the core-voltage conversion chain. The P5V_VME rail, also from the P1 connector, feeds the main 3.3 V domain. A separate P3V3_VME rail is present on the backplane but has no on-board consumers.

From P12V, a TPS62125 buck converter (IC32) generates the 5VREG housekeeping rail. 5VREG powers the two Infineon IRPS5401M digital PMICs (IC30, IC31), the TDA21535 power stage (IC29), and the TPS74801 LDO (IC22). IC29 produces the P0V85 core rail for the FPGA. IC30 generates P1V8 (two paralleled channels C and D), VCC_PSPLL (internal LDO), and drives IC29 via its PWM_A output. IC31 generates MGT_1V2, MGT_1V8, P1V2, MGT_0V9, and MGT_0V85 (internal LDO). IC22 post-regulates 5VREG down to P2V5 for DDR4 VPP.

From P5V_VME, the LMZ31704 power module (IC40) produces P3V3, the largest rail on the board with over 600 pins and 225 decoupling capacitors. P3V3 is further filtered through two 220-ohm-at-100-MHz ferrite beads (L13, L14) to create the P3V3_CLK sub-rail for the clock synthesizers (IC18, IC60), the DAC (IC10), and the voltage reference (IC12). The TPS51200 DDR termination regulator (IC24) derives VTT_DDR4-PS from P1V2.

Smaller filtered sub-rails include VCC_PSDDR_PLL and VCC_PSADC, both derived from P1V8 through individual 120-ohm-at-100-MHz ferrite beads (L5, L6), and PSADC_AGND, an isolated analog ground for the FPGA PS-side ADC connected to GND through a 600-ohm-at-100-MHz ferrite bead (L2).

Power sequencing is managed through the enable chain of the IRPS5401M devices. IC32 starts unconditionally when P12V is present (EN tied to VIN). Its PG output on net 5VPG enables IC22 (EN pin). IC30 is enabled by the 5VREG rail through R212 to its EN_L, EN_A, EN_C, and EN_D pins. IC31 is gated by the P1V8AUX_PG signal from IC30 pin PG_D, which drives IC31 EN_L, EN_A, EN_B, EN_C, and EN_D. IC29 EN is tied to P3V3, so it starts once the 3.3 V rail is live. IC24 PGOOD drives the FPGA PS_POR_B pin, establishing the final power-good handshake to the processor. IC40 starts whenever P5V_VME is applied because its INH/UVLO pin is intentionally unconnected, relying on the internal pull-up.

anyway, enjoy see if the explanations help in designing your own power architecture if you're using high end FPGAs.

Wonderful design by u/Teusner called Caiman. https://github.com/Teusner/Caiman. He/she was nice enough to post the KiCad for processing when asking for a review on r/PCB. 168 pages of reports and checks. Caiman received a Tomachie score of 81 out of 100, which is very good. with suggestions on design-for-test improvements.The full AI Assisted overview is here:

https://tomachie.com/r/0f916018-f374-4e59-b553-af2aa1a2918a/caiman_report.html

AI-Assisted: The output inductor L1 is 3.3 uH in a Wuerth MAPI-4020 package. The datasheet recommends 2.2 uH to 10 uH for most applications, so 3.3 uH is within the recommended range. The output capacitance on the +5V rail consists of four 22 uF ceramics (C4, C5, C7, C8 in 0603), four 100 nF ceramics (C47, C49, C50, C51 in 0603), one 10 uF ceramic (C6, 0603), and one 470 uF electrolytic (C48). The total ceramic output capacitance is approximately 98 uF (four times 22 uF plus one 10 uF plus four times 100 nF), which substantially exceeds the datasheet recommended 22 uF minimum. The 470 uF electrolytic provides additional bulk energy storage. This is a well-decoupled output rail.

Some design issues are raised on shield being connected to logic GND, some need of caps near the SD Card interface, consider a different inductor value, and some ESD/EMC compliance issues to review. All and all a very well designed schematic, the layout for the RF is probably the trickiest part of the design. Some excerpts:

AI-Assisted: The design has a flat ground architecture with no separation between chassis ground and signal ground. All four mounting holes (H1 through H4) bond directly to GND. This is acceptable for a small embedded system that operates inside a shielded enclosure, but if the product is used without an enclosure or with a non-conductive housing, the lack of a chassis ground domain means there is no controlled ESD discharge path to earth ground. Per IEC 61000-4-2, the ground reference plane setup is critical for repeatable ESD immunity testing.

The power input at J7 has appropriate TVS protection (D1, SMBJ33CA) consistent with the TI LM74700-Q1 datasheet application circuit. The battery input at J8 and the VCC input at J9 lack TVS protection. If these connectors are user-accessible, transient protection should be investigated.