u/black_panther8502

What's Friday Night plan guys , edaina unte cheppandi, ee lokam lo bore kotti poyela unnam

Hi everyone, I’m currently working on an academic FPGA project involving ECC-256, ECC-384, and ECC-528 signing and verification algorithms, mainly focusing on modular arithmetic architectures for low-latency and resource optimized designs.

My target operating frequency is around 400–500 MHz, and I’m looking for any relevant research papers, publications, GitHub repositories, or references related to efficient modular arithmetic techniques for ECC on FPGA platforms. Any guidance or pointers would be greatly appreciated. This is purely for academic and research purposes.

Thanks in advance!

Hello everyone,

I didn't thought I would post this here, but I have no option left with. So I am trying to implement RSA 3072 bit for fpga in vhdl. The main part in RSA is modular exponentiation as everyone know. I am currently referring to a phd thesis (link provided) . I am stuck at 3072 bit arithmetic that is addition and subtraction of such huge bits, even though they are only 4-5 long additions , I didn't find any algo to implement it in hardware as that many bit addition cannot be done in a single clock cycle. And also i need help in doing A mod B without huge addition or subtraction. I also need to precompute N inverse , currently implemented one algo but it has 3072 bit long additions.

I know this is too much to ask from you , but I am in need for algo's and their implementation.I am also ready to take any new suggestion for implementing modular exponentiation if you know better algo for fpga which you have implemented or you have worked on.

reference link