r/Verilog

Verilog Learning Resources
▲ 34 r/Verilog+1 crossposts

Verilog Learning Resources

For the past few months I was looking everywhere to find some resources to learn Verilog while also building projects. After a lot of time spent online, I was able to find some really good resources that would help you understand it by also helping you build projects alongside.

You would require any pre-requisites for the following courses, but you'll be able to understand them fairly well considering they're some excellent resources.

First one are the Onur Mutlu Lectures on Digital Design and Computer Architecture. This will help build the concept that'll be applied in your codes.

The second one is Digital Circuit Design using Verilog lectures by Anas Salah Eddin. His lectures are very detailed and simple to understand. He also builds several projects such as FIFO and UART by the end of the playlist.

The final resource I would suggest is the popular DDCA Book by Harris and Harris (whichever edition you'd prefer, MIPS, ARM, RISC-V)

It isn't mandatory for you to follow these resources in order, but I'd suggest you to cover either the book or Onur Mutlu's Lectures before jumping on to Verilog lectures, or at least build a proper conceptual base, since that would help you to follow through those Verilog lectures.

Though the lectures follow with Verilog, the book provides SystemVerilog examples and exercises. They aren't much different from one another. Once you've understood Verilog, there's barely much to do for SV.

I hope someone who needs these resources finally finds them, just like I was looking for them a few months ago.

u/stardust_0205 — 10 days ago
▲ 4 r/Verilog+1 crossposts

I built an open-source GUI that generates UPF from power intent you draw on your real RTL hierarchy

Hi all,

I've been working on power intent for several years, and kept hitting the same thing: UPF is written by hand, line by line, and the actual power architecture only exists in your head.

It's especially tough for people new to low-power design.

So over the last ~6 months I built Power Intent Studio, an open-source (Apache 2.0) desktop app, with AI as my development partner. You load your RTL and .lib macros, the real elaborated hierarchy appears, and you build the power intent on top of it:

  • power domains, supply sets, power switches, isolation, retention, level shifters
  • a power state table (exported as a modern power state group or a legacy PST)
  • UPF 3.0/3.1 and CPF 2.0/2.1 generation
  • loading an existing UPF and mapping it back onto the design; unrecognised syntax is reported with its line number instead of failing

RTL goes through open-source front ends: slang for Verilog/SystemVerilog, GHDL + Yosys for VHDL, liberty-parser for .lib. The repo includes a SystemVerilog SoC example (aura_top) with six domains, three switches and SRAM macros, and its full generated UPF, so you can judge the output yourself.

What it is NOT: a sign-off checker. It doesn't verify that your power intent is correct; it writes what you draw. Structural checks are one of the ideas I'd love to explore next.

I'd really value feedback from people who write UPF every day:

  • What would make this useful in your flow?
  • Throw your UPF at it. What doesn't load?

Repo: https://github.com/mikespyke17/power-intent-studio

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u/Pasulu — 9 days ago
▲ 7 r/Verilog+2 crossposts

Standard milestone flow for Lint, CDC, and Synthesis? (P0.3 to P1.0)

I want to make sure my understanding of our project milestone flow aligns with broader industry standards. I’d love some feedback or corrections from those with more tape-out experience.

Here is how I understand the flow:

P0.3 (Early RTL): Basic Lint runs continuously/nightly to catch obvious typos and syntax issues as code is being written.

P0.5 (RTL Design Correction / Freeze): This is the major, formal Lint sign-off. Code is feature-complete. This is when we deep-dive, group errors by tag, fix actual RTL bugs, and negotiate targeted waivers with IP designers.

P0.8 (Verification & Pre-Synthesis Sign-off): CDC checks are finalized and signed off. The RTL is officially locked.

P1.0 (Synthesis Complete): The clean, signed-off P0.8 RTL is handed over to run Logical Synthesis (e.g., Design Compiler) to generate the gate-level netlist.

My questions:

Does this P0.3 ➡️ P0.5 ➡️ P0.8 ➡️ P1.0 progression for Lint/CDC/Synthesis match what you see in standard ASIC flows?

At what exact point do you usually start running CDC? Is it strictly after P0.5 Lint is clean, or does it run in parallel?

Thanks in advance

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u/Adventurous_Bell3550 — 11 days ago