r/Verilog

A lot of students want to enter semiconductor design, but many get confused about where to start.

Some jump directly into physical design.
Some start with RTL.
Some try analog first.
Some only watch videos and collect certificates.

In my opinion, a beginner-friendly roadmap should look something like this:

1. CMOS Understand transistors, basic circuits, SPICE simulation, and how devices behave.
2. RTL Learn Verilog, digital logic design, testbenches, and simulation.
3. Physical Design Understand synthesis, floorplanning, placement, CTS, routing, timing, and how RTL becomes layout.
4. Physical Verification Learn DRC, LVS, antenna checks, density, PEX, and what it means to make a design tapeout-ready.

For someone who already knows RTL and basic physical design, jumping directly into an internship-style physical design project may make more sense than restarting from zero.

The bigger point is this:

Interest in semiconductors is not enough anymore. Students need proof — GitHub work, simulation results, reports, screenshots, debug notes, and projects they can explain.

Curious to hear from people already working in VLSI / semiconductors:

Would you change this order?
Should beginners start with CMOS first, or RTL first?
What would you tell a student who wants to enter chip design seriously in 2026?

Hi everyone,

I've been working on a side project to learn FPGA architecture design and hardware image processing.

The project is a Local Interaction Processor (LIP): an 8×8 parallel image-processing fabric written entirely in Verilog.

Current features:

- 64 processing elements (8×8)

- Erosion

- Dilation

- Opening

- Closing

- Uniformity

- Roughness

- Programmable 3×3 structuring element masks

- Multiple simulation testbenches

- Yosys ASIC synthesis

- ECP5 FPGA synthesis

Architecture:

frame_in

↓

lip_top

↓

lip_array

↓

64 × lip_pe

↓

minmax_engine + threshold_engine

↓

frame_out

One thing that surprised me during FPGA synthesis is that the design is extremely compute-heavy.

Resource utilization before placement:

- Total LUT4: 54298 / 83640 (64%)

- Logic LUT: 35034 / 83640 (41%)

- Carry LUT: 19264 / 83640 (23%)

- DFF: 2048 / 83640 (2%)

- RAM usage: 0%

This kind of makes sense since the architecture is basically a giant parallel neighborhood-comparison machine with almost no memory hierarchy.

Right now I'm trying to figure out where to take the project next.

Some ideas I had:

1. OpenLane ASIC flow

2. Add BRAM + streaming interfaces

3. AXI integration

4. Deploy onto a real FPGA board

5. Try cloud-hosted FPGA platforms

My questions for experienced FPGA engineers:

- Is a LUT-heavy / memory-light architecture normal for this kind of workload?

- Is there a better architectural approach for morphological image processing?

- What would be the most logical next step if the goal was turning this into a "real" accelerator instead of just an RTL project?

I'd appreciate any suggestions or critiques.

Repo: https://github.com/abhi15-bose-max/LIP

Also the zenodo link ( IDK if its working, first time putting on zenodo): https://zenodo.org/records/20822134