r/Verilog

Teaching others will revise my basics. nothing else. Anybody interested hit me up. I can do 1 hr a day, everyday.

What are some important and useful wensites for vlsi engineers ????

Does verilator , find combinational loops , i mean i tried it on a .sv file and it finds them through UNOPTFLAT but when i try to run it on bigger files I doesn't catch them any suggestions.

+ I need to force include a .vh verilog header file, how to do it?