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r/Verilog

▲ 2 r/Verilog

Packages and Pre-processors?

Hi all I am working on a UVM testbench with the following structure:

filelist:

proj_package.sv

tbtop.sv

proj_package.sv:

package abc;

`include "param.sv"

endpackage

param.sv:

`define ADD 400

tbtop.sv:

import abc::*;

`include "testlist.sv"

testlist.sv:

`include "sample_test.sv"

sample_test.sv:

write_reg(ADD, 5);

I had some questions:

  1. Does `include "param.sv" inside package abc make the ADD macro available to files that later do import abc::*?

  2. If I write import abc::* inside base_test, can derived tests use ADD?

  3. Is a `define ever considered a member of a SystemVerilog package, or are macros completely separate from package scope

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u/Snoo51532 — 3 days ago
▲ 4 r/Verilog+1 crossposts

Help with Iverilog installation

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iverilog latest version downloded from bleyer.org shows this pls help me, is it false positive or else , also if can give correct download link ,im trying for vscode + iverilog + gtkwave , pls help im total noob and begineer to verilog

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u/Hot_Interview_7762 — 5 days ago
▲ 41 r/Verilog+2 crossposts

Some good notes for Digital VLSI and associated Concepts

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u/Good_Layer_4623 — 6 days ago
▲ 6 r/Verilog

What's the actual difference between using a mux-style ternary (a ? b : c) vs if/else chains in an FSM?

I've been grinding through the Lemmings FSM problems (HDLBits) and after several rounds of debugging my own if/else based next_state logic, I saw a solution that wrote the entire transition logic as nested ternaries, like this:

next_state = (ground)? (dig)? DIGGING_L : (bump_left)? RIGHT : LEFT : FALLING_L;

vs what I wrote, which was a wall of if (bump_left && ground && !dig) ... else if (...).

Both should synthesize to muxes under the hood, so is this purely a style thing, or is there an actual reason (readability, synthesis efficiency, fewer bugs from priority ordering, whatever) that experienced RTL designers reach for nested ternaries/case-based muxes over long if/else chains?

Personally I use if/else because it's easier for me to debug step-by-step. Curious whether that's actually a worse habit long-term, or if it's genuinely just style.

Would appreciate hearing from anyone who does this for a living, since apparently this one was written by an NVIDIA engineer and it's making me rethink how I structure combinational logic in general.

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u/MessageEmpty2594 — 6 days ago
▲ 14 r/Verilog+2 crossposts

Vivado Ip

​

I am currently working on a project using the VCU108 board, for which I was using the 1G and 10G Ethernet IPs in Vivado.

The IP licenses/access I was previously using have now expired. Instead of renewing the licenses, I would like to know whether it is possible to obtain the Verilog/source code of these IPs so that I can continue working on the project.

is there is any other way to obtain the required Verilog code?

Thank you.

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u/LearnHard_20 — 9 days ago
▲ 5 r/Verilog+4 crossposts

👋Welcome to r/SVUVM

What the sub is about:

SystemVerilog and UVM. RTL basics, testbenches, verification methodology, all the way up to full UVM environments.

What to Post:

- projects / resumes

- personal notes

- learning resources

- debugging help

- concept breakdown

- interview/exam questions

What not to post:

- pirated books

- pirated video

- cracked licensed software

- any discussions regarding piracy

Happy Learning.

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u/hieg_siel — 10 days ago
▲ 4 r/Verilog

Deferred Assertions and Icarus Verilog

Hi guys,

I’m learning sv for a SAR ADC and am trying to build a RNM model of my CDAC so I can test my logic. I wanted a block that checks if I’m in an illegal state (multiple switches on that would short-circuit the CDAC, complementary signals not matching, etc). My issue is it seems like whenever I edit a signal in my initial block it immediately starts checking the assertions, even though I have it set up so in that same time “block” other signals will change too. So I’ll turn one switch on and the other off, but the simulator will see that first switch turn on and flag it.

My understanding would be this is what a deferred assertion would be used for. But my simulator (iverilog) doesn’t support them. Is there a workaround for this? Or another sim I could use on an Apple Silicon Mac? I have a thinkpad I use for stuff that can’t run on my mac (like quartus) but like my mac much more and don’t want to move my neovim setup over if I don’t have to.

Obviously a beginner so please let me know if any part of my approach is wrong / any solutions.

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u/Gatordude365 — 14 days ago