u/New_Today172

Hi everyone,

I've been working on a side project to learn FPGA architecture design and hardware image processing.

The project is a Local Interaction Processor (LIP): an 8×8 parallel image-processing fabric written entirely in Verilog.

Current features:

- 64 processing elements (8×8)

- Erosion

- Dilation

- Opening

- Closing

- Uniformity

- Roughness

- Programmable 3×3 structuring element masks

- Multiple simulation testbenches

- Yosys ASIC synthesis

- ECP5 FPGA synthesis

Architecture:

frame_in

↓

lip_top

↓

lip_array

↓

64 × lip_pe

↓

minmax_engine + threshold_engine

↓

frame_out

One thing that surprised me during FPGA synthesis is that the design is extremely compute-heavy.

Resource utilization before placement:

- Total LUT4: 54298 / 83640 (64%)

- Logic LUT: 35034 / 83640 (41%)

- Carry LUT: 19264 / 83640 (23%)

- DFF: 2048 / 83640 (2%)

- RAM usage: 0%

This kind of makes sense since the architecture is basically a giant parallel neighborhood-comparison machine with almost no memory hierarchy.

Right now I'm trying to figure out where to take the project next.

Some ideas I had:

1. OpenLane ASIC flow

2. Add BRAM + streaming interfaces

3. AXI integration

4. Deploy onto a real FPGA board

5. Try cloud-hosted FPGA platforms

My questions for experienced FPGA engineers:

- Is a LUT-heavy / memory-light architecture normal for this kind of workload?

- Is there a better architectural approach for morphological image processing?

- What would be the most logical next step if the goal was turning this into a "real" accelerator instead of just an RTL project?

I'd appreciate any suggestions or critiques.

Repo: https://github.com/abhi15-bose-max/LIP

Also the zenodo link ( IDK if its working, first time putting on zenodo): https://zenodo.org/records/20822134

Although these projects are written in Verilog rather than VHDL, I thought the architecture side might be interesting to this community.

I've been learning digital design and built two small spatial-computing style fabrics:

• A programmable morphology accelerator using local 3×3 neighborhood logic

• A wavefront-routing fabric where shortest-path information propagates across a mesh of cells

Both were simulated, synthesized through OpenLane, and taken all the way to GDSII.

I'd appreciate feedback on the RTL architecture and whether similar approaches have been explored in larger FPGA or ASIC systems.

Repos:

https://github.com/abhi15-bose-max/morphology-fabric-asic

https://github.com/abhi15-bose-max/wavefront-routing-fabric

I've been teaching myself digital design and OpenLane recently and built a couple of small spatial-computing style hardware projects.

One is a programmable morphology accelerator based on local 3×3 neighborhood interactions.

The other is a wavefront-routing fabric where routing costs propagate across a mesh of cells and automatically route around obstacles.

Both are currently implemented in Verilog RTL and synthesized to SKY130 through OpenLane.

I originally built them as learning projects, but I'm curious whether similar architectures have been explored on larger FPGA fabrics or CGRA-style systems.

Repos:

https://github.com/abhi15-bose-max/morphology-fabric-asic

https://github.com/abhi15-bose-max/wavefront-routing-fabric

Any feedback or suggestions for improvement would be appreciated.

Since November of 2023 , life feels stock , as if it doesn't progress, will the upcoming Rahu antardasha be any better?? I lost my academic edge in this mars antardasha , I am working on personal projects now , I just wanna know if things will get better.