u/Economy-Win-105

Infosys is coming to our college for recruitment, and I need to prepare my resume for it.
The offered salary packages are:
Specialist Programmer L3 (Trainee): ₹21 LPA
Specialist Programmer L2 (Trainee): ₹16 LPA
Specialist Programmer L1 (Trainee): ₹10 LPA + ₹1 Lakh Joining Bonus
Digital Specialist Engineer (Trainee): ₹6.25 LPA + ₹75,000 Joining Bonus
Can you help me build a strong resume? Also, what skills and topics should I learn and prepare to maximize my chances of getting selected?

Hi everyone,
I’m an ECE student from India with a 7.7 CGPA and strong interest in:
Verilog/SystemVerilog
FPGA Design
Digital Design
Computer Architecture
Embedded Systems
SoC Design
I’ve been working on FPGA projects using Vivado and enjoy hardware design much more than general software development.
I’m confused between:
Doing an MS directly after graduation (Computer Engineering, Embedded Systems, VLSI, Computer Architecture)
Getting a core hardware job first (FPGA/RTL/Embedded/VLSI), gaining 2–3 years of experience, and then pursuing an MS
Considering the current semiconductor job market and hiring trends, what would you recommend?
I’d love to hear from people working in FPGA, RTL, ASIC, verification, embedded systems, or computer architecture:
Is an MS worth doing immediately?
Does industry experience provide a better ROI before a master’s?
Which countries currently offer the best opportunities in this field?
Thanks! Any advice would be appreciated.

I am new to Verilog, so what are the best Youtube channels to learn HDL as a beginner?

Working on a PYNQ-Z2 real-time image processing project:

USB Webcam → OpenCV → AXI DMA (MM2S) → Dual-Port BRAM → FPGA Filters (Sobel/Blur/Threshold) → RGB2DVI → HDMI

Current status:

* 64×64 grayscale video is displaying on HDMI.
* DMA, BRAM write/read, and HDMI output are working.
* BRAM depth = 4096 bytes, image size = 4096 bytes.

Known concerns / possible remaining issues:

1. AXI DMA length register appears limited to 14 bits. Current 4096-byte frame works, but moving to 128×128 (16384 bytes) or larger resolutions may hit transfer-size limitations.
2. BRAM read side (pclk) and write side (fclk) run independently with no frame-sync handshake. Could this cause tearing or occasional frame corruption?
3. Single-buffer BRAM architecture currently used. Would ping-pong buffering or double buffering be recommended?
4. Looking for the best way to scale from 64×64 to 128×128 and eventually higher resolutions while keeping HDMI output stable.
5. Any recommendations for BRAM pointer management, DMA frame boundaries (`TLAST` handling), or clock-domain synchronization between DMA and display paths?

Would appreciate feedback from anyone who has implemented AXI DMA + BRAM + HDMI pipelines on Zynq/PYNQ platforms.

We’re building a PYNQ-Z2 FPGA image-processing system (Webcam → DMA → BRAM → FPGA Filters → HDMI) and are considering simultaneously streaming the original 720p webcam feed over Wi-Fi; what’s the best way to do this given the board has only one USB host port?