▲ 36 r/RISCV
RISC-V RVV Vector Performance Benchmarks With The SpacemiT K3 SoC
phoronix.comu/camel-cdr- — 4 days ago
▲ 34 r/RISCV
The Boot Chain of a RISC-V Board: From Silicon to Ubuntu 26.04
blog.ludovic.devu/camel-cdr- — 27 days ago
▲ 30 r/RISCV
SpacemiT X100 clang benchmark with and without RVC
I tested the impact of disabling RVC on the SpacemiT X100 with clang. Enabling RVC resulted in a roughly 10% performance improvement, which is higher than I expected.
AFAIK while the X100 supports a handful of fusion pairs, those aren't compressed only. (bitwise+bitwise, mul+add, add+load/store, slli+sr*i) The fetch bandwidth is 16-byte / cycle (probably, because it's based on C910), so enough to saturate the 4-way decode without RVC, but may struggle to keep it feed, in branchy code. Though the Cortex-A76, also has a 16-byte fetch with a 4-wide decode.
So I'm not sure what the tells us about RVC exactly. The additional L1I misses don't feel like they'd impact perf that much on their own.
u/camel-cdr- — 2 months ago
▲ 19 r/RISCV
The RTL will be released under OpenHW soon (probably tomorrow):
u/camel-cdr- — 2 months ago
▲ 9 r/RISCV
SiFive previously announced that Kinara licensed their X280 IP for their Ara-2 NPU. Turns out Kinara was recently acquired by NXP, who now seem to sell their NPU, see attached data sheet.
It's not 100% confirmed these are X280 cores, but as mentioned the Kinara connection and:
> Ara240 implements a vector processing cluster consisting of two vector cores (RISC-V architecture with RV64IMACV extensions). Vector length of 512-bits is supported for INT8, INT16, INT32, FP16, and FP32 data formats. The vector cores complement Neural Network Processors and can be used to execute non-neural network tasks such as post-processing functions. The vector processors are not end-user programmable and the set of functions executable on the vector cores are limited to the ones packaged as part of Ara SDK.
u/camel-cdr- — 2 months ago