Creating an Ai based on Amadeus from steins gate. Using CORES
I've had this idea, which other's have not really done to incorporate. But.
If I make this Amadeus ai, What about I buy different esp32s, Each working as something I call "cores"
By my definition: Cores, which is short for
- Cognitive
- Output &
- Reactions
- Evaluation
- System
The logic is pretty self explanatory. Each core will have it's own function:
An emotional core, A morality core, a cognition core, a Morality core and a curiosity core.
These cores, as they suggest will be attached onto Amadeus In a way that can give her more contextual awareness. I'd like to take opinions. Pre development of course.
u/franticblood — 12 days ago
IRQ Dispatcher code showcase and explanation.
Hello everybody! A few days ago I made a post talking about using an array of linked lists as a method for IRQ dispatching. I made a video after I finished the code explaining how it works. I hope you all enjoy this <3
The video goes through the assembly, and C code used to make this as well as the Diagram and how it went from being a diagram -> actual code
u/franticblood — 13 days ago
▲ 11 r/steinsgate
SPOILERS IN THIS POST!!!
Seriously what the fuck... I just reached episode 16 on the Anime.. Just to realize Daru is Suzuha amane's dad? The naming convention kind of thew it off but I thought it was irrelevant at first.. How did this perv even get married 😭
u/franticblood — 15 days ago
An Array of linked lists as An IRQ dispatcher For a custom X86 operating system.
Hello everyone, I am currently working on an IRQ dispatcher for my X86 operating system and would like to share my idea on how it will work. There are 7 different groupings for my IDT vectors.
0x00–0x1F |
CPU exceptions |
|---|---|
0x20 |
Local APIC timer |
0x21–0x2F |
Reserved for legacy IRQ compatibility |
0x30–0xEF |
External device interrupts, allocated by the kernel |
0xF0–0xFE |
Reserved for kernel/APIC-specific interrupts |
0xFF |
Local APIC spurious interrupt |
Each group goes from a specific value until another value,
for example The CPU exceptions go from 0-31, Meaning the first array will hold 0-31 Lists
Array 2 will Hold 1 etc etc
I would like to show the diagram on how it will work as:
This is simply a mental map on how indexing will work, Each array has it's OWN group of lists, so there cant be cross indexing.
This data structure is a hybrid between the Array and linked list data structure (In this case it is a singly linked list)
Where it creates multiple arrays, where each array Has it's own sequence of linked lists.
It merges two linear Data structures.
If you'd like to learn more feel free to check the link below:
https://www.geeksforgeeks.org/cpp/array-of-linked-list-in-c-cpp/
u/franticblood — 18 days ago