u/groman434

Hello guys,

I have been FPGA hobbyist for a long time. Unfortunately, I find extremely hard to motivate myself to work on my pet projects. So I thought that maybe someone is looking for extra help. I can pick up some dull and mundane tasks if this improve my FPGA skills. Also, some compensation would be nice, but this is not a must.

Few words about me - embedded SW engineer with almost 15 years of experience, predominantly in cellular communications and DSP.

Hello,

I am just a hobbyist who really detest using any sort of GUI. On top of that, I love to have a deep understanding of what I actually do instead of "click here, next click here and it will work magically (trust me bro, I am an engineer)" approach.

I wanted to create a simple block design with Microblaze connected to a few basic peripherals (GPIO, UART) via AXI interconnect IP. However, I struggled a lot with connecting some pins, namely ACLK and ARESETN. Even though there were clearly connected (I even confirmed this in the dreaded GUI), Vivado claimed otherwise. Therefore I wanted to create an alternative design using "apply_bd_automation". However, it seems lime the list of all rules accepted by this command is not available anywhere. I could bodge something up using AI, but this is not what I call proper understanding.

Do you have any suggestions of how to approach this problem?

Hello,

I have a problem with M_ACLK and M_ARESETN lines. I prefer to work completely in Tcl console and I avoid using GUI as much as possible. I use Vivado 2024.2.

First, I created a clock wizard using the following

create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0

Next, I created reset controller and did some basic routing

create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 reset_0
connect_bd_net [get_bd_ports /RESET] [get_bd_pins /reset_0/ext_reset_in]
connect_bd_net [get_bd_pins /clk_wiz_0/clk_out1] [get_bd_pins /reset_0/slowest_sync_clk]
connect_bd_net [get_bd_pins /clk_wiz_0/locked] [get_bd_pins /reset_0/dcm_locked]

Finally, I created AXI interconnect and connected everything together

connect_bd_net [get_bd_pins /clk_wiz_0/clk_out1] [get_bd_pins /axi_interconnect_0/ACLK]
connect_bd_net [get_bd_pins /clk_wiz_0/clk_out1] [get_bd_pins /axi_interconnect_0/M00_ACLK]
connect_bd_net [get_bd_pins /clk_wiz_0/clk_out1] [get_bd_pins /axi_interconnect_0/M01_ACLK]
connect_bd_net [get_bd_pins /clk_wiz_0/clk_out1] [get_bd_pins /axi_interconnect_0/S00_ACLK]
connect_bd_net [get_bd_pins /reset_0/interconnect_aresetn] [get_bd_pins /axi_interconnect_0/ARESETN]
connect_bd_net [get_bd_pins /reset_0/interconnect_aresetn] [get_bd_pins /axi_interconnect_0/M00_ARESETN]
connect_bd_net [get_bd_pins /reset_0/interconnect_aresetn] [get_bd_pins /axi_interconnect_0/M01_ARESETN]
connect_bd_net [get_bd_pins /reset_0/interconnect_aresetn] [get_bd_pins /axi_interconnect_0/S00_ARESETN]

I omitted some pieces of Tcl code for brevity. At first glance, everything looks okay. validate_bd_design does not complain about anything. But then, when I run the synthesis, I get the following warning messages

WARNING: [Synth 8-7129] Port M00_ACLK in module design_1_axi_interconnect_0_0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port M00_ARESETN in module design_1_axi_interconnect_0_0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port M01_ACLK in module design_1_axi_interconnect_0_0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port M01_ARESETN in module design_1_axi_interconnect_0_0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port S00_ACLK in module design_1_axi_interconnect_0_0 is either unconnected or has no load
WARNING: [Synth 8-7129] Port S00_ARESETN in module design_1_axi_interconnect_0_0 is either unconnected or has no load

I double-checked everything I could, including HDL wrapper. Everything looks okay to me. I am not able to figure out what's exactly wrong, so I will appreciate your help.

Kind regards,