u/seenhokage

I've been working on a microkernel called Robu and thought I'd finally share it here.

It's written from scratch in C and assembly, and the main thing I'm interested in is seeing how far I can take the microkernel approach without letting IPC and context switching become painfully expensive.

A lot of the design is inspired by the L4 family, especially things like synchronous IPC, register-based messages, timeslice donation and lazy scheduling.

The kernel is meant to stay pretty small, with things like drivers, filesystems, networking and paging living outside of it in userspace.

Right now I'm mainly working on x86_64, although I want to support ARM and RISC-V as well.

There's still a lot to do, but the basic pieces are starting to come together. I'm putting it out here mainly to get some feedback from people who are into OS development and microkernels.

GitHub: https://github.com/bayar17/robu_microkernel

I've started work on Robu, a microkernel in C and assembly. Sharing the design now because I'd rather get told what's wrong with it before I've written 20k lines against it.

The premise is that microkernel performance is entirely determined by four paths — IPC, page fault resolution, context switching, and interrupt delivery — so those are what I designed first:

• IPC: register-based short messages, synchronous rendezvous, timeslice donation from sender to receiver
• VM: page faults delegated to a user-space pager; kernel arbitrates mappings, holds no policy
• Scheduling: lazy scheduling with direct switch — the IPC-to-ready-thread case never touches the run queue
• Interrupts: delivered as messages to user-space handlers on the same path as ordinary IPC

To get ahead of the obvious comment: yes, these are L4 ideas. Liedtke's work is why anyone thinks this is achievable. Robu shares no code with any L4 and I'm not treating one as a reference implementation — I'm building it from the constraints up, partly to find out which of those ideas I actually understand versus have merely read about.

Targets are armv7/armv8, x86_64, i386/i486, riscv32/riscv64. Currently on x86_64 under QEMU, macOS host. Perf target is the low end — 111 MHz Pentium, ESP32-class RISC-V — because a modern desktop hides everything. POSIX-like API planned above the kernel. MIT.

Robu Microkernel Repository

Specific thing I'd like opinions on: for the direct-switch path, where do you draw the line between "fast path in assembly" and "keep it in C so it stays portable across six architectures"? I keep moving that line.