4-layer PCB Review Update: ESP32 LoRa GPS Tracking & transmitting device.
Hello everyone,
This is a continuation of my previous post asking for a review of my first PCB Design for this project. Like I said in my previous post, I am very new to PCB design and have been learning as I go, would love some feedback on my design, especially regards to the power circuit I have.
Stackup:
-Top Layer Signals + Components:
-GND Plane
-VCC (3.3V) Plane
-Bottom Layer Signals
Main changes:
- I realized from the EByte LoRa datasheet that 3.3V input would not achieve maximum transmission range and that I would need a 5V input to do so. Therefore I added in a boost transformer to have a consistent 5V supply for the LoRa, sine my input voltage from the LiPo battery is only ~3.7V. My concern with this is the length of the 5V trace and the BAT line from the LiPo connector cuts through the width of the board and might interfere with other bottom & top layer lines when peak current is reached during transmisson, ~1200mAh per datasheet.
- Is it a good idea to route the 5V trace as I did? I tried avoiding routing anything underneath the LoRa as per the datasheet as well. I did consider completely redoing the layout but thought I would close off this version as is then V2 would be focused on layout and routing improvements.
- I moved the GPS closer to the center edge as recommended by the datasheet. I plan on using a ceramic antenna to place directly underneath the GPS, hence the opening next the the U.FL connector.
- Double checked the GPS & LoRa datasheet, a GND copper pour underneath them is fine and with limited effect.
- Changed the Boot & Reset buttons to 90° mounted buttons for better access and smaller size.
- Added a via fence to the RF trace of the LoRa and checked with JLCPCBs impedance calculator to match the RF trace thickness with the 50 ohm impedance requirement, about ~1.5mm trace width.
- Made sure there was enough space for standoffs to be placed for a future enclosure.
- I made other changes as specified in my previous post by a few commenters, much appreciated!
A few question/concerns of mine now:
- Will the 5V trace be affected by the surrounding VCC copper pour or vice versa? What would be a good work around to this? I did consider a 6 layer stackup with 5V and GND2 as the 2 extra layers to avoid the long trace and use blind vias to connect the inner layer, but seemed like overkill.
- I have a few small copper pour GND "islands" but all are connected with at least one via to the GND plane, is this good enough to avoid parasitic interference? Or would proper via stitching be advised? Again, they are small, I pasted an image of the pour for reference. Would via stitching be advised for other reasons such as, for e.g., the 5V line cutting through the VCC plane
- Is there a general rule on spacing between traces of different types? Ive been following guides online, but they sometimes seem arbitrary?
Of course, any other suggestions or changes is much appreciated and thank you in advance!!
Edit: Just realized one of the LoRa corners overlaps with one of the screw holes of the OLED screen, will fix that!